Internal Interrupts; Interrupt Operations; Figure 3.2 Block Diagram Of Interrupt Controller - Renesas H8/3847R Series Hardware Manual

Section 3 Exception Handling
3.3.4

Internal Interrupts

There are 24 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in
IENR1 or IENR2. All these interrupts can be masked by setting the I bit to 1 in CCR. When
internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 20 to 10
are assigned to these interrupts. Table 3.2 shows the order of priority of interrupts from on-chip
peripheral modules.
3.3.5

Interrupt Operations

Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the
interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance.
External or
internal
interrupts
External
interrupts or
internal
interrupt
enable
signals
Rev. 6.00 Aug 04, 2006 page 108 of 680
REJ09B0145-0600

Figure 3.2 Block Diagram of Interrupt Controller

Interrupt controller
I CCR (CPU)
Interrupt
request