Input/Output Pins; Figure 5.1 Block Diagram Of Interrupt Controller; Table 5.1 Pin Configuration - Renesas H8SX/1500 Series Hardware Manual

Section 5 Interrupt Controller
A block diagram of the interrupt controller is shown in figure 5.1.
NMI input
IRQ input
Internal interrupt sources
WOVI to SSTXI2
[Legend]
INTCR:
CPUPCR:
ISCR:
IER:
5.2

Input/Output Pins

Table 5.1 shows the pin configuration of the interrupt controller.
Table 5.1 Pin Configuration
Name
NMI
IRQ14 to IRQ0
Rev. 3.00 Mar. 14, 2006 Page 88 of 804
REJ09B0104-0300
INTM1, INTM0
INTCR
NMIEG
NMI input unit
ISR
IRQ input unit
ISCR IER SSIER
Source selecter
Interrupt controller
Interrupt control register
CPU priority control register
IRQ sense control register
IRQ enable register

Figure 5.1 Block Diagram of Interrupt Controller

I/O Function
Input Nonmaskable External Interrupt
Rising or falling edge can be selected.
Input Maskable External Interrupts
Rising, falling, or both edges, or level sensing, can be selected.
IPR
I
I2 to I0
CPU
interrupt request
CPU
vector
Priority
decision unit
DMAC
activation
enable
CPUPCR
IRQ status register
ISR:
Software standby release IRQ enable register
SSIER:
Interrupt priority register
IPR:
CPU
CCR
EXR
DMAC
DMAC priority
control
DMDR