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REGISTER 0—N REGISTER
MUXOUT
TR1
Tx/Rx
0
TRANSMIT
1
RECEIVE
U1
UART_MODE
0
DISABLED
1
ENABLED
M3
M2
M1
MUXOUT
0
0
0
REGULATOR_READY (DEFAULT)
0
0
1
FILTER_CAL_COMPLETE
0
1
0
DIGITAL_LOCK_DETECT
0
1
1
RSSI_READY
1
0
0
Tx_Rx
1
0
1
LOGIC_ZERO
1
1
0
TRISTATE
1
1
1
LOGIC_ONE
•
The RF output frequency is calculated as follows:
For direct output,
⎛
=
×
⎜
RF
PFD
INTEGER
OUT
⎝
With RF_DIVIDE_BY_2 (Register 1, Bit DB18) enabled,
⎛
=
×
×
⎜
RF
PFD
0
5 .
OUT
⎝
•
In UART/SPI mode, the TxRxCLK pin is used to input
the transmitted data. The received data is available on the
TxRxDATA pin.
INTEGER_N
N8
N7
N6
N5
N4
0
0
0
1
0
0
0
0
1
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 62. Register 0—N Register Map
FRACTIONAL
_
N
+
_
N
15
2
FRACTIONAL
+
INTEGER
_
N
15
2
FRACTIONAL_N
M15
0
0
0
.
.
.
1
1
1
1
INTEGER_N
N3
N2
N1
DIVIDE RATIO
1
1
1
23
0
0
0
24
.
.
.
.
.
.
.
.
.
.
.
.
1
0
1
253
1
1
0
254
1
1
1
255
•
In the MUXOUT map (Bits[DB31:DB29]), FILTER_CAL_
COMPLETE indicates when a coarse or coarse plus fine IF
filter calibration has finished. DIGITAL_LOCK_DETECT
⎞
indicates when the PLL has locked. RSSI_READY indicates
⎟
⎠
that the RSSI signal has settled and an RSSI readback can
be performed. Tx_Rx gives the status of Bit DB27 in this
register, which can be used to control an external Tx/Rx
⎞
_
N
switch.
⎟
⎠
Rev. 0 | Page 45 of 60
M14
M13
...
M3
M2
M1
0
0
...
0
0
0
0
0
...
0
0
1
0
1
0
0
0
...
.
.
...
.
.
.
.
.
...
.
.
.
.
.
...
.
.
.
1
1
...
1
0
0
1
1
...
1
0
1
1
1
...
1
1
0
1
1
1
1
...
1
ADF7021-V
ADDRESS
BITS
FRACTIONAL_N
DIVIDE RATIO
0
1
2
.
.
.
32,764
32,765
32,766
32,767
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