Table 15-3 Branches And Stages Evaluated By The Processor - ARM Cortex-M3 Technical Reference Manual

Branch Instruction
B <imm>
B <imm>
BL
BLX LR
BX LR
MOV PC, LR
ADD PC
BLX
BX
CBZ, CBNZ
ISB
LDR PC
LDM to PC
MOV PC
ARM DDI 0337G
Unrestricted Access
The ALU register based branches and LSU PC modifying instructions are recognized
as conditional branches, b0011, if they are present in IT blocks. Otherwise they are
recognized as unconditional branches, b0101.
Instruction size Stage branch target is issued
16 bits Decode
32 bits Decode
32 bits Decode
16 bits Decode
16 bits Decode
16 bits Decode
32 bits Execute
16 bits Execute
16 bits Execute
16 bits Execute
16 bits Execute
32 bits Execute
32 bits Execute
32 bits Execute
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Table 15-3 Branches and stages evaluated by the processor

Non-Confidential
Embedded Trace Macrocell Interface
Notes
-
-
If LR is not being written during
decode.
If LR is not being written during
decode.
If LR is not being written during
decode.
If LR is not being written during
decode.
-
If LR is not the source register or
if LR is being written during
decode.
If LR is not the source register or
if LR is being written during
decode.
-
-
-
-
If LR is not the source register or
if LR is being written during
decode and LR is the source
register.
15-7