ST STM32L4+ Series Reference Manual page 1145

RM0432
•
Interruptible message digest computation, on a per-block basis
–
–
35.3 HASH implementation
The devices have a single instance of HASH peripheral.
35.4 HASH functional description
35.4.1 HASH block diagram
Figure 279
hash_dma
Re-loadable digest registers
Hashing computation suspend/resume mechanism, including DMA
shows the block diagram of the hash processor.
Figure 279. HASH block diagram
AHB
interface
hash_hclk
DMA
interface
IRQ
hash_it
interface
Banked Registers
HASH_DIN
Data, key
HASH_HRx
HASH_SR
Status
HASH_CR
Control
HASH_STR
Start
HASH_CSRx
Control Logic
RM0432 Rev 6
Hash processor (HASH)
HASH
Core
(SHA-1,
Secure digest
SHA-224,
SHA-256,
MD5)
+
HMAC
logic
Suspend/Resume
MSv62405V3
1145/2301
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