ST STM32L4+ Series Reference Manual page 1138

AES hardware accelerator (AES)
34.7.6 AES key register 1 (AES_KEYR1)
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29
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15 14 13
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Bits 31:0 KEY[63:32]: Cryptographic key, bits [63:32]
Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
34.7.7 AES key register 2 (AES_KEYR2)
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29
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15 14 13
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Bits 31:0 KEY[95:64]: Cryptographic key, bits [95:64]
Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
34.7.8 AES key register 3 (AES_KEYR3)
Address offset: 0x1C
Reset value: 0x0000 0000
31 30 29 28
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15 14 13 12
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Bits 31:0 KEY[127:96]: Cryptographic key, bits [127:96]
Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
1138/2301
28 27 26 25
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12 11 10 9
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28 27 26 25
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12 11 10 9
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27 26 25
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11 10 9
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24 23 22
KEY[63:48]
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8 7 6
KEY[47:32]
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24 23 22
KEY[95:80]
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8 7 6
KEY[79:64]
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24 23 22 21
KEY[127:112]
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8 7 6 5
KEY[111:96]
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RM0432 Rev 6
21 20 19 18
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5 4 3 2
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21 20 19 18
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5 4 3 2
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20 19 18
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4 3 2
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RM0432
17 16
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1 0
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17 16
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1 0
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17 16
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1 0
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