ST STM32L4+ Series Reference Manual page 1134

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AES hardware accelerator (AES)

Bits 4:3 MODE[1:0]: AES operating mode

This bitfield selects the AES operating mode:

00: Mode 1: encryption

01: Mode 2: key derivation (or key preparation for ECB/CBC decryption)

10: Mode 3: decryption

11: Mode 4: key derivation then single decryption

Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the

write access and it is not cleared by that write access. Any attempt to selecting Mode 4 while either

ECB or CBC chaining mode is not selected, defaults to effective selection of Mode 3. It is not

possible to select a Mode 3 following a Mode 4.

Bits 2:1 DATATYPE[1:0]: Data type selection

This bitfield defines the format of data written in the AES_DINR register or read from the

AES_DOUTR register, through selecting the mode of data swapping:

01: Half-word (16-bit)

10: Byte (8-bit)

For more details, refer to

Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the

write access and it is not cleared by that write access.

Bit 0 EN: AES enable

This bit enables/disables the AES peripheral:

At any moment, clearing then setting the bit re-initializes the AES peripheral.

This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2)

and upon the completion of GCM/GMAC/CCM initial phase.

AES status register (AES_SR)

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Section 34.4.13: AES data registers and data

RM0432 Rev 6

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