ST STM32L4+ Series Reference Manual page 1144

Hash processor (HASH)
35 Hash processor (HASH)
35.1 Introduction
The hash processor is a fully compliant implementation of the secure hash algorithm
(SHA-1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and
the HMAC (keyed-hash message authentication code) algorithm. HMAC is suitable for
applications requiring message authentication.
The hash processor computes FIPS (Federal Information Processing Standards) approved
digests of length of 160, 224, 256 bits, for messages of up to (2
128-bit digests for the MD5 algorithm.
35.2 HASH main features
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Suitable for data authentication applications, compliant with:
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Fast computation of SHA-1, SHA-224, SHA-256, and MD5
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Corresponding 32-bit words of the digest from consecutive message blocks are added
to each other to form the digest of the whole message
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Automatic padding to complete the input bit string to fit digest minimum block size of
512 bits (16 × 32 bits)
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Single 32-bit input register associated to an internal input FIFO, corresponding to one
block size
• AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB
error is generated)
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8 × 32-bit words (H0 to H7) for output message digest
• Automatic data flow control with support of direct memory access (DMA) using one
channel.
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Only single DMA transfers are supported
1144/2301
Federal Information Processing Standards Publication FIPS PUB 180-4, Secure
Hash Standard (SHA-1 and SHA-2 family)
Federal Information Processing Standards Publication FIPS PUB 186-4, Digital
Signature Standard (DSS)
Internet Engineering Task Force (IETF) Request For Comments RFC 1321, MD5
Message-Digest Algorithm
Internet Engineering Task Force (IETF) Request For Comments RFC 2104,
HMAC: Keyed-Hashing for Message Authentication and Federal Information
Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message
Authentication Code (HMAC)
82 (respectively 66) clock cycles for processing one 512-bit block of data using
SHA-1 (respectively SHA-256) algorithm
66 clock cycles for processing one 512-bit block of data using MD5 algorithm
Automatic 32-bit words swapping to comply with the internal little-endian
representation of the input bit-string
Word swapping supported: bits, bytes, half-words and 32-bit words
RM0432 Rev 6
RM0432
64
– 1) bits. It also computes