ST STM32L4+ Series Reference Manual page 1152

Hash processor (HASH)
no swapping mode (DATATYPE=00 in HASH_CR), the following data must be loaded
sequentially into HASH_DIN register:
1. Inner hash key input (lenght=64, i.e. no padding), specified by NIST. As key
lenght=64, LKEY bit is set to 0 in HASH_CR register
00010203 04050607 08090A0B 0C0D0E0F 10111213 14151617
18191A1B 1C1D1E1F 20212223 24252627 28292A2B 2C2D2E2F
30313233 34353637 38393A3B 3C3D3E3F
2. Message input (lenght=34, i.e. padding required). HASH_STR must be set to 0x20 to
start message padding and inner hash computation (see 'U' as don't care)
53616D70 6C65206D 65737361 67652066 6F72206B 65796C65
6E3D626C 6F636B6C 656EUUUU
3. Outer hash key input (lenght=64, i.e. no padding). A key identical to the inner hash key
is entered here.
4. Final outer hash computing is then performed by the HASH. The HMAC-SHA1 digest
result is available in the HASH_HRx registers (x = 0 to 4), as shown below:
HASH_HR0 = 0x5FD596EE
HASH_HR1 = 0x78D5553C
HASH_HR2 = 0x8FF4E72D
HASH_HR3 = 0x266DFD19
HASH_HR4 = 0x2366DA29
1152/2301 RM0432 Rev 6
RM0432