RM0432
In accordance to the kind of data to be processed (e.g. byte swapping when data are ASCII
text stream) there must be a bit, byte, half-word or no swapping operation to be performed
on data from the input FIFO before entering the little-endian hash processing core.
Figure 280
from one 32-bit words popped into input FIFO by the driver, according to the DATATYPE
bitfield in the HASH control register (HASH_CR).
HASH_DIN data endianness when bit swapping is disabled (DATATYPE=00) can be
described as following: the least significant bit of the message has to be at MSB position in
the first word entered into the hash processor, the 32nd bit of the bit string has to be at MSB
position in the second word entered into the hash processor and so on.
DATATYPE "00": no swapping
written first!
LSB
Word0
bit31
bit0
M0
M31
LSB
DATATYPE "01": 16-bit or half-word swapping
written first!
LSB
Word0
bit31
bit16
bit15
M0
M15
M16
LSB
DATATYPE "10": 8-bit or byte swapping
written first!
LSB
Word0
bit31..24
bit23..16 bit15..8
M0..7
M8..15 M16..23
LSB
DATATYPE "11": bit swapping
written first!
LSB
Word0
bit31 bit30 bit29
bit2 bit1 bit0
M0 M1 M2
M29 M30 M31 M32 M33 M34
LSB
shows how the hash processing core 32-bit data block M0...31 is constructed
Figure 280. Message data swapping feature
System interface
Word1
bit31
bit0
M32
M63
HASH core interface
Word1
bit0
bit31
bit16
bit15
M31
M32
M47
M48
Word1
bit7..0
bit31..24
bit23..16 bit15..8
M24..31
Word1
bit31 bit30 bit29
bit2 bit1 bit0
M61 M62 M63
Word2
bit31
bit31
bit0
M64
M95
M96
System interface
Word2
bit0
bit31
bit16
bit15
M63
HASH core interface
System interface
Word2
bit7..0
bit31..24
bit23..16 bit15..8
HASH core interface
System interface
Word2
HASH core interface
RM0432 Rev 6
Hash processor (HASH)
MSB
Word3
bit0
M127
MSB
Word3
bit0
bit31
bit16
bit15
M96
M111
M112
Word3
bit7..0
bit31..24
bit23..16 bit15..8
M96..103
M112..119
Word3
bit31bit30 bit29
bit2 bit1 bit0
M125
M96 M97 M98
MSB
bit0
M127
MSB
MSB
bit7..0
M120..127
MSB
MSB
M126
M127
MSB
MSv41984V3
1147/2301
1166
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