ST STM32L4+ Series Reference Manual page 1109

RM0432
ECB/CBC decryption sequence
The sequence of events to perform an AES ECB/CBC decryption is as follows (More detail
in Section
1. Follow the steps described in
order to prepare the decryption key in AES core.
2. Select the Mode 3 by setting to 10 the MODE[1:0] bitfield of the AES_CR register and
select ECB or CBC chaining mode by setting the CHMOD[2:0] bitfield of the AES_CR
register to 000 or 001, respectively. Data type can also be defined, using
DATATYPE[1:0] bitfield. KEYSIZE bitfield must be kept as-is.
3. Write the AES_IVRx registers with the initialization vector (required in CBC mode only).
4. Enable AES by setting the EN bit of the AES_CR register.
5. Write the AES_DINR register four times to input the cipher text (MSB first), as shown in
Figure
6. Wait until the CCF flag is set in the AES_SR register.
7. Read the AES_DOUTR register four times to get the plain text (MSB first), as shown in
Figure
8. Repeat steps
WR
CT3
MSB
4 write operations into
AES_DINR[31:0]
PT = plaintext = 4 words (PT3, ... , PT0)
CT = ciphertext = 4 words (CT3, ... , CT0)
Suspend/resume operations in ECB/CBC modes
To suspend the processing of a message, proceed as follows:
1. If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN
bit of the AES_CR register.
2. If DMA is not used, read four times the AES_DOUTR register to save the last
processed block. If DMA is used, wait until the CCF flag is set in the AES_SR register
then stop the DMA transfers from the OUT FIFO by clearing the DMAOUTEN bit of the
AES_CR register.
3. If DMA is not used, poll the CCF flag of the AES_SR register until it becomes 1
(computation completed).
4. Clear the CCF flag by setting the CCFC bit of the AES_CR register.
5. Save initialization vector registers (only required in CBC mode as AES_IVRx registers
are altered during the data processing).
34.4.4).
266.
266. Then clear the CCF flag by setting the CCFC bit of the AES_CR register.
5-6-7 to process all the blocks encrypted with the same key.
Figure 266. ECB/CBC decryption (Mode 3)
WR WR WR
CT2 CT1 CT0
LSB
Input phase
Section 34.4.5: AES decryption round key
Wait until flag CCF = 1
Computation phase
RM0432 Rev 6
AES hardware accelerator (AES)
preparation, in
RD RD
PT3 PT2 PT1
MSB
Output phase
4 read operations from
AES_DOUTR[31:0]
RD RD
PT0
LSB
MS18938V3
1109/2301
1143