ST STM32L4+ Series Reference Manual page 1130

AES hardware accelerator (AES)
transiting back to data transferring managed by software. See
in ECB/CBC modes
34.4.17 AES error management
AES configuration can be changed at any moment by clearing the EN bit of the AES_CR
register.
Read error flag (RDERR)
Unexpected read attempt of the AES_DOUTR register sets the RDERR flag of the AES_SR
register, and returns zero.
RDERR is triggered during the computation phase or during the input phase.
Note: AES is not disabled upon a RDERR error detection and continues processing.
An interrupt is generated if the ERRIE bit of the AES_CR register is set. For more details,
refer to Section 34.5: AES
The RDERR flag is cleared by setting the ERRIE bit of the AES_CR register.
Write error flag (WDERR)
Unexpected write attempt of the AES_DINR register sets the WRERR flag of the AES_SR
register, and has no effect on the AES_DINR register. The WRERR is triggered during the
computation phase or during the output phase.
Note: AES is not disabled after a WRERR error detection and continues processing.
An interrupt is generated if the ERRIE bit of the AES_CR register is set. For more details,
refer to Section 34.5: AES
The WRERR flag is cleared by setting the ERRC bit of the AES_CR register.
34.5 AES interrupts
Individual maskable interrupt sources generated by the AES peripheral signal the following
events:
• computation completed
•
read error
• write error
•
key error
The individual sources are combined into the common interrupt signal aes_it that connects
to NVIC (nested vectored interrupt controller). Each can individually be enabled/disabled, by
setting/clearing the corresponding enable bit of the AES_CR register, and cleared by setting
the corresponding bit of the AES_CR register.
The status of each can be read from the AES_SR register.
Table 231
1130/2301
in Section 34.4.8: AES basic chaining modes (ECB, CBC)
interrupts.
interrupts.
gives a summary of the interrupt sources, their event flags and enable bits.
RM0432 Rev 6
RM0432
Suspend/resume operations
as example.