Contention Between Compare Matches A And B - Renesas H8S/2319 series Hardware Manual

Renesas 16-bit single-chip microcomputer
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10.6.4

Contention between Compare Matches A and B

If compare match events A and B occur at the same time, the 8-bit timer operates in accordance
with the priorities for the output statuses set for compare match A and compare match B, as shown
in table 10-4.
Table 10-4 Timer Output Priorities
Output Setting
Toggle output
1 output
0 output
No change
10.6.5
Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 10-5 shows the
relationship between the timing at which the internal clock is switched (by writing to the CKS1
and CKS0 bits) and the TCNT operation.
When the TCNT clock is generated from an internal clock, the falling edge of the internal clock
pulse is detected. If clock switching causes a change from high to low level, as shown in case 3 in
table 10-5, a TCNT clock pulse is generated on the assumption that the switchover is a falling
edge. This increments TCNT.
The erroneous incrementation can also happen when switching between internal and external
clocks.
Priority
High
Low
Rev. 5.00, 12/03, page 403 of 1088

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