Contention Between Compare Matches A And B; Figure 12.12 Contention Between Tcor Write And Compare Match; Table 12.4 Timer Output Priorities - Renesas H8S/2368 Series Hardware Manual

φ
Address
Internal write signal
TCNT
TCOR
Compare match signal

Figure 12.12 Contention between TCOR Write and Compare Match

12.8.4

Contention between Compare Matches A and B

If compare match events A and B occur at the same time, the 8-bit timer operates in accordance
with the priorities for the output statuses set for compare match A and compare match B, as shown
in table 12.4.

Table 12.4 Timer Output Priorities

Output Setting
Toggle output
1 output
0 output
No change
Rev. 2.00, 05/03, page 490 of 820
TCOR write cycle by CPU
T
1
TCOR address
N
N
Priority
High
Low
T
2
N+1
M
TCOR write data
Inhibited