Conflict Between Buffer Register Write And Input Capture - Renesas H8SX/1650 Hardware Manual

Section 9 16-Bit Timer Pulse Unit (TPU)
9.9.10

Conflict between Buffer Register Write and Input Capture

If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 9.52 shows the timing in this case.
P
Address
Write
Input capture signal
TCNT
TGR
Buffer register
Figure 9.52 Conflict between Buffer Register Write and Input Capture
Rev.2.00 Jun. 28, 2007 Page 386 of 666
REJ09B0311-0200
Buffer register write cycle
T T
1 2
Buffer register
address
N
M N
M