Conflict Between Buffer Register Write And Input Capture - Renesas H8S/2100 Series Hardware Manual

10.8.9

Conflict between Buffer Register Write and Input Capture

If the input capture signal is generated in the T
operation takes precedence and the write to the buffer register is not performed. Figure 10.50
shows the timing in this case.
φ
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register
Figure 10.50 Conflict between Buffer Register Write and Input Capture
Section 10 16-Bit Timer Pulse Unit (TPU)
state of a buffer register write cycle, the buffer
2
Buffer register write cycle
T1 T2
Buffer register
address
N
M N
M
Rev. 1.00 May 09, 2008 Page 287 of 954
REJ09B0462-0100