10.9.10 Contention Between Buffer Register Write And Input Capture; Figure 10.51 Contention Between Buffer Register Write And Input Capture - Renesas H8S Series Hardware Manual

10.9.10 Contention between Buffer Register Write and Input Capture

If an input capture signal is generated in the T
operation takes precedence and the write to the buffer register is not performed.
Figure 10.51 shows the timing in this case.
φ
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register

Figure 10.51 Contention between Buffer Register Write and Input Capture

Section 10 16-Bit Timer Pulse Unit (TPU)
state of a buffer register write cycle, the buffer
2
Buffer register write cycle
T T
1 2
Buffer register
address
N
M N
M
Rev. 6.00 Mar 15, 2006 page 241 of 570
REJ09B0211-0600