Table of Contents
Advertisement
Contention between Buffer Register Write and Input Capture:
If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes priority and the write to the buffer register is not performed. Figure 12.53 shows
the timing in this case.
φ
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register
Figure 12.53 Contention between Buffer Register Write and Input Capture
Contention between Overflow/Underflow and Counter Clearing:
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes priority. Figure 12.54 shows the operation timing when a TGR
compare match is specified as the clearing source, and H'FFFF is set in TGR.
Buffer register write cycle
T
T
1
2
Buffer register
address
N
M
N
M
Rev. 1.00, 09/03, page 361 of 704
Advertisement
Table of Contents
