Conflict Between Tcnt Write And Increment Operations; Conflict Between Tgr Write And Compare Match - Renesas H8SX/1650 Hardware Manual

9.9.5

Conflict between TCNT Write and Increment Operations

If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented. Figure 9.47 shows the timing in this case.
P
Address
Write
TCNT input
clock
TCNT
Figure 9.47 Conflict between TCNT Write and Increment Operations
9.9.6

Conflict between TGR Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is disabled. A compare match also does not occur when the same
value as before is written.
Figure 9.48 shows the timing in this case.
P
Address
Write
Compare match
signal
TCNT
TGR
Figure 9.48 Conflict between TGR Write and Compare Match
Section 9 16-Bit Timer Pulse Unit (TPU)
TCNT write cycle
T T
1 2
TCNT address
N M
TCNT write data
TGR write cycle
T T
1 2
TGR address
N N
N M
TGR write data
Rev.2.00 Jun. 28, 2007 Page 383 of 666
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