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10.8.5
Conflict between TGR Write and Compare Match
If a compare match occurs in the T
and the compare match signal is inhibited. A compare match does not occur even if the same value
as before is written. Figure 10.46 shows the timing in this case.
φ
Address
Write signal
Compare
match signal
TCNT
TGR
Figure 10.46 Conflict between TGR Write and Compare Match
10.8.6
Conflict between Buffer Register Write and Compare Match
If a compare match occurs in the T
buffer operation will be the data prior to the write. Figure 10.47 shows the timing in this case.
φ
Address
Write signal
Compare
match signal
Buffer
register
TGR
Figure 10.47 Conflict between Buffer Register Write and Compare Match
state of a TGR write cycle, the TGR write takes precedence
2
TGR write cycle
T1
T2
TGR address
N
N
TGR write data
state of a TGR write cycle, the data transferred to TGR by the
2
TGR write cycle
T1
T2
Buffer register
address
N
Section 10 16-Bit Timer Pulse Unit (TPU)
Prohibited
N+1
M
Buffer register write data
M
N
Rev. 1.00 May 09, 2008 Page 285 of 954
REJ09B0462-0100
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