10.10.6 Contention Between Tgr Write And Compare Match; 10.10.7 Contention Between Buffer Register Write And Compare Match; Figure 10.47 Contention Between Tgr Write And Compare Match - Renesas H8S/2368 Series Hardware Manual

10.10.6 Contention between TGR Write and Compare Match

If a compare match occurs in the T
and the compare match signal is disabled. A compare match also does not occur when the same
value as before is written.
Figure 10.47 shows the timing in this case.
φ
Address
Write signal
Compare
match signal
TCNT
TGR

Figure 10.47 Contention between TGR Write and Compare Match

10.10.7 Contention between Buffer Register Write and Compare Match

If a compare match occurs in the T
buffer operation will be the data prior to the write.
Figure 10.48 shows the timing in this case.
state of a TGR write cycle, the TGR write takes precedence
2
TGR write cycle
T T
1
TGR address
N
N
TGR write data
state of a TGR write cycle, the data transferred to TGR by the
2
2
Disabled
N + 1
M
Rev. 2.00, 05/03, page 447 of 820