Figure 12.49 Contention Between Tgr Write And Compare Match; Figure 12.50 Contention Between Buffer Register Write And Compare Match - Renesas H8S/2437 Hardware Manual

Contention between TGR Write and Compare Match:
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes priority and
the compare match signal is disabled. A compare match does not occur even if the same value as
before is written to. Figure 12.49 shows the timing in this case.
φ
Address
Write signal
Compare
match signal
TCNT
TGR

Figure 12.49 Contention between TGR Write and Compare Match

Contention between Buffer Register Write and Compare Match:
If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the
buffer operation will be the write data. Figure 12.50 shows the timing in this case.
φ
Address
Write signal
Compare
match signal
Buffer
register
TGR

Figure 12.50 Contention between Buffer Register Write and Compare Match

TGR write cycle
T T
1 2
TGR address
N N+1
N M
TGR write data
TGR write cycle
T T
1 2
Buffer register
address
N M
N
Disabled
Buffer register write data
Rev. 1.00, 09/03, page 359 of 704