Contention Between Tgr Write And Compare Match; Figure 10.47 Contention Between Tgr Write And Compare Match - Renesas H8S Series Hardware Manual

10.9.6

Contention between TGR Write and Compare Match

If a compare match occurs in the T
and the compare match signal is inhibited. A compare match does not occur even if the previous
value is written.
Figure 10.47 shows the timing in this case.
φ
Address
Write signal
Compare
match signal
TCNT
TGR

Figure 10.47 Contention between TGR Write and Compare Match

state of a TGR write cycle, the TGR write takes precedence
2
TGR write cycle
T T
1 2
TGR address
N
N
TGR write data
Section 10 16-Bit Timer Pulse Unit (TPU)
Prohibited
N + 1
M
Rev. 6.00 Mar 15, 2006 page 237 of 570
REJ09B0211-0600