Chapter 1 Introduction; Overview - Analog Devices ADSP-2106x SHARC User Manual

Introduction 1
1.1

OVERVIEW

The ADSP-2106x SHARC—Super Harvard Architecture Computer—is a
high-performance 32-bit digital signal processor for speech, sound, graphics,
and imaging applications. The SHARC builds on the ADSP-21000 Family
DSP core to form a complete system-on-a-chip, adding a dual-ported on-chip
SRAM and integrated I/O peripherals supported by a dedicated I/O bus.
With its on-chip instruction cache, the processor can execute every
instruction in a single cycle. Four independent buses for dual data,
instructions, and I/O, plus crossbar switch memory connections, comprise
the Super Harvard Architecture of the ADSP-2106x.
The ADSP-2106x SHARC represents a new standard of integration for digital
signal processors, combining a high-performance floating-point DSP core
with integrated, on-chip features including a host processor interface, DMA
controller, serial ports, and link port and shared bus connectivity for glueless
DSP multiprocessing.
Figure 1.1 illustrates the Super Harvard Architecture of the ADSP-2106x:
a crossbar bus switch connecting the core numeric processor to an
independent I/O processor, dual-ported memory, and parallel system bus
port. Figure 1.2 shows a detailed block diagram of the processor, illustrating
the following architectural features:
• 32-Bit IEEE Floating-Point Computation Units—Multiplier, ALU, and Shifter
• Data Register File
• Data Address Generators (DAG1, DAG2)
• Program Sequencer with Instruction Cache
• Interval Timer
• Dual-Ported SRAM
• External Port for Interfacing to Off-Chip Memory & Peripherals
• Host Port & Multiprocessor Interface
• DMA Controller
• Serial Ports
• Link Ports
• JTAG Test Access Port
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