Chip Select Signals; Figure 6.6 Csn Signal Output Timing (N = 0 To 7) - Renesas H8S/2368 Series Hardware Manual

Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In externally expanded
mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-
chip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when
the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in
external space.
When area 7 external space is accessed, the CS7 signal can be output.
Only the basic bus interface can be used for the area 7 memory interface.
6.4.4

Chip Select Signals

This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when
the corresponding external space area is accessed. Figure 6.6 shows an example of CS0 to CS7
signals output timing.
Enabling or disabling of CS0 to CS7 signals output is set by the data direction register (DDR) bit
for the port corresponding to the CS0 to CS7 pins.
In expanded mode with on-chip ROM disabled, the CS0 pin is placed in the output state after a
reset. Pins CS1 to CS7 are placed in the input state after a reset and so the corresponding DDR bits
should be set to 1 when outputting signals CS1 to CS7.
In expanded mode with on-chip ROM enabled, pins CS0 to CS7 are all placed in the input state
after a reset and so the corresponding DDR bits should be set to 1 when outputting signals CS0 to
CS7.
When areas 2 to 5 are designated as DRAM space, outputs CS2 is used as RAS signals.
Note: The DRAM interface is not supported by the H8S/2366.
Address bus
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Figure 6.6 CSn CSn Signal Output Timing (n = 0 to 7) CSn CSn
Bus cycle
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Area n external address
Rev. 2.00, 05/03, page 137 of 820
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