Reso Signal Output Timing; Interrupt Sources; Figure 11.5 Output Timing Of Reso Signal; Table 11.2 Wdt Interrupt Source - Renesas H8S/2111B Hardware Manual

RESO Signal Output Timing

11.4.3
When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the
RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time,
the low level signal is output from the RESO pin. The timing is shown in figure 11.5.
φ
TCNT
Overflow signal
(internal signal)
OVF
RESO signal
Internal reset
signal
11.5

Interrupt Sources

During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is
generated by an overflow.

Table 11.2 WDT Interrupt Source

Name
WOVI
Rev. 1.00, 05/04, page 230 of 544
H'FF

Figure 11.5 Output Timing of RESO signal

Interrupt Source
TCNT overflow
H'00
132 states
518 states
Interrupt Flag
OVF