Reso Signal Output Timing; Interrupt Sources; Figure 15.5 Output Timing Of Reso Signal; Table 15.2 Wdt Interrupt Source - Renesas H8S/2158 User Manual

Section 15 Watchdog Timer (WDT)

RESO Signal Output Timing

RESO RESO RESO
15.4.3
When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the
RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time,
the low level signal is output from the RESO pin. The timing is shown in figure 15.5.
φ
TCNT
Overflow signal
(internal signal)
OVF
RESO signal
Internal reset
signal
15.5

Interrupt Sources

During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is
generated by an overflow.

Table 15.2 WDT Interrupt Source

Name Interrupt Source
WOVI TCNT overflow
Rev. 3.00 Jan 25, 2006 page 382 of 872
REJ09B0286-0300
H'FF
Figure 15.5 Output Timing of RESO
Interrupt Flag
OVF
H'00
132 states
518 states
RESO Signal RESO RESO
DTC Activation
Not possible