Terminal Count Output When Dma Transfer Is Complete; Timing Example Of Terminal Count Signals (Dmtco3 To Dmtco0); Example Of Terminal Count Signal Output (Dmtco3 To Dmtco0) - Renesas NU85E Preliminary User's Manual

7.11 Terminal Count Output When DMA Transfer Is Complete

The terminal count signal (DMTCOn) becomes active for only one clock in the final DMA transfer cycle (n = 3 to 0).
Figure 7-26. Timing Example of Terminal Count Signals (DMTCO3 to DMTCO0)
Remark n = 3 to 0
During 2-cycle transfer, the signal becomes active for one clock at the beginning of the last write cycle.
During flyby transfer, the signal becomes active for one clock at the beginning of the last transfer cycle.
Figure 7-27. Example of Terminal Count Signal Output (DMTCO3 to DMTCO0)
VBCLK (Input)
DMTCOn (Output)
VBCLK (Input)
DMTCOn (Output)
Remark n = 3 to 0
176
CHAPTER 7 DMAC
DMARQn (Input)
DMTCOn (Output)
CPU CPU
(1) Two-cycle transfer
Two-cycle transfer (last)
Read cycle
(2) Flyby transfer
Preliminary User's Manual A14874EJ3V0UM
CPU DMAn DMAn DMAn CPU
DMA channel n
terminal count
Write cycle
Flyby transfer (last)