Renesas SH7780 Series Microcontrollers Manuals

Manuals and User Guides for Renesas SH7780 Series Microcontrollers. We have 1 Renesas SH7780 Series Microcontrollers manual available for free PDF download: Hardware Manual

Renesas SH7780 Series Hardware Manual (1340 pages)

Renesas 32-Bit RISC Microcomputer SuperH RISC Engine Family

Brand: Renesas | Category: Computer Hardware | Size: 7.76 MB

General Precautions on Handling of Product
4
Preface
6
Table of Contents
9
Section 1 Overview

51
- SH7780 Features
  51
  - Section 1 Overview
    52
  - Table 1.1 SH7780 Features
    52
  - Contents
    54
- Block Diagram
  59
- Figure 1.1 SH7780 Block Diagram
  59
- Pin Arrangement
  60
- Figure 1.2 SH7780 Pin Arrangement
  60
- Pin Functions
  61
- Table 1.2 Pin Functions
  61
- Memory Address Map
  77
- Figure 1.3 Physical Address Space of SH7780
  78
- Figure 1.4 Relationship between AREASEL Bits and Memory Address Map
  79
- Superhyway Bus
  80
- Superhyway Memory (Superhyway RAM)
  81
Section 2 Programming Model

83
- Data Formats
  83
- Figure 2.1 Data Formats
  83
- Register Descriptions
  84
- Memory-Mapped Registers
  96
- Data Formats in Registers
  97
- Figure 2.6 Formats of Byte Data and Word Data in Register
  97
- Data Formats in Memory
  98
- Figure 2.7 Data Formats in Memory
  98
- Processing States
  99
- Figure 2.8 Processing State Transitions
  99
- Usage Note
  100
  - Notes on Self-Modified Codes
    100
Section 3 Instruction Set

101
Section 4 Pipelining

123
Section 5 Exception Handling

147
- Summary of Exception Handling
  147
- Register Descriptions
  147
- Exception Handling Functions
  151
  - Exception Handling Flow
    151
  - Exception Handling Vector Addresses
    151
- Exception Types and Priorities
  152
- Table 5.3 Exceptions
  152
- Exception Flow
  154
- Description of Exceptions
  158
  - Resets
    158
  - General Exceptions
    160
  - Interrupts
    174
  - Priority Order with Multiple Exceptions
    175
- Usage Notes
  177
Section 6 Floating-Point Unit (FPU)

179
- Features
  179
- Data Formats
  180
- Register Descriptions
  185
- Rounding
  191
- Floating-Point Exceptions
  192
- Graphics Support Functions
  194
  - Geometric Operation Instructions
    194
  - Pair Single-Precision Data Transfer
    195
Section 7 Memory Management Unit (MMU)

197
- Overview of MMU
  197
  - Address Spaces
    199
  - Figure 7.1 Role of MMU
    199
  - Figure 7.2 Virtual Address Space (at in MMUCR = 0)
    200
  - Figure 7.3 Virtual Address Space (at in MMUCR = 1)
    201
  - Figure 7.4 P4 Area
    203
  - Figure 7.5 Physical Address Space
    204
- Register Descriptions
  206
- TLB Functions
  217
- MMU Functions
  223
  - MMU Hardware Management
    223
  - MMU Software Management
    223
  - MMU Instruction (LDTLB)
    224
  - Hardware ITLB Miss Handling
    225
  - Figure 7.11 Operation of LDTLB Instruction
    225
  - Avoiding Synonym Problems
    226
- MMU Exceptions
  227
- Memory-Mapped TLB Configuration
  233
  - ITLB Address Array
    234
  - Figure 7.12 Memory-Mapped ITLB Address Array
    234
  - ITLB Data Array
    235
  - Figure 7.13 Memory-Mapped ITLB Data Array
    235
  - UTLB Address Array
    236
  - UTLB Data Array
    237
  - Figure 7.14 Memory-Mapped UTLB Address Array
    237
- 32-Bit Address Extended Mode
  238
Section 8 Caches

247
- Features
  247
- Table 8.2 Store Queue Features
  247
- Figure 8.1 Configuration of Operand Cache (OC)
  248
- Figure 8.2 Configuration of Instruction Cache (IC)
  249
- Register Descriptions
  250
- Operand Cache Operation
  257
  - Read Operation
    257
  - Prefetch Operation
    258
  - Write Operation
    259
  - Write-Back Buffer
    261
  - Write-Through Buffer
    261
  - OC Two-Way Mode
    261
  - Figure 8.3 Configuration of Write-Back Buffer
    261
  - Figure 8.4 Configuration of Write-Through Buffer
    261
- Instruction Cache Operation
  262
  - Read Operation
    262
  - Prefetch Operation
    263
  - IC Two-Way Mode
    263
- Cache Operation Instruction
  264
  - Coherency between Cache and External Memory
    264
  - Prefetch Operation
    265
- Memory-Mapped Cache Configuration
  266
  - IC Address Array
    267
  - Figure 8.5 Memory-Mapped IC Address Array
    268
  - IC Data Array
    269
  - Figure 8.6 Memory-Mapped IC Data Array
    269
  - OC Address Array
    270
  - Figure 8.7 Memory-Mapped OC Address Array
    271
  - OC Data Array
    272
  - Figure 8.8 Memory-Mapped OC Data Array
    272
- Store Queues
  273
  - SQ Configuration
    273
  - Writing to SQ
    273
  - Figure 8.9 Store Queue Configuration
    273
  - Transfer to External Memory
    274
  - Determination of SQ Access Exception
    275
  - Reading from SQ
    275
- Notes on Using 32-Bit Address Extended Mode
  276
Section 9 L Memory

277
- Features
  277
- Register Descriptions
  278
- Operation
  288
  - Access from the CPU and FPU
    288
  - Access from the Superhyway Bus Master Module
    288
  - Block Transfer
    288
- L Memory Protective Functions
  290
- Table 9.4 Protective Function Exceptions to Access L Memory
  290
- Usage Notes
  291
  - Page Conflict
    291
  - L Memory Coherency
    291
  - Sleep Mode
    291
- Note on Using 32-Bit Address Extended Mode
  291
Section 10 Interrupt Controller (INTC)

293
Section 11 Local Bus State Controller (LBSC)

365
Section 12 DDR-SDRAM Interface (DDRIF)

451
Section 13 PCI Controller (PCIC)

493
Section 14 Direct Memory Access Controller (DMAC)

607
Section 15 Clock Pulse Generator (CPG)

663
- Features
  663
- Figure 15.1 Block Diagram of CPG
  664
- Input/Output Pins
  666
- Table 15.1 CPG Pin Configuration
  666
- Clock Operating Modes
  667
- Table 15.2 Clock Operating Modes
  667
- Register Descriptions
  668
- Notes on Board Design
  672
- Figure 15.2 Points for Attention When Using Crystal Resonator
  672
- Figure 15.3 Points for Attention When Using PLL and DLL Circuit
  673
Section 16 Watchdog Timer and Reset

675
Section 17 Power-Down Mode

693
- Features
  693
  - Types of Power-Down Modes
    693
  - Table 17.1 Power-Down Modes
    694
- Input/Output Pins
  695
- Register Descriptions
  695
- Sleep Mode
  698
  - Transition to Sleep Mode
    698
  - Cancellation of Sleep Mode
    698
- Module Standby State
  699
  - Transition to Module Standby Mode
    699
  - Cancellation of Module Standby Mode and Resume
    699
- DDR-SDRAM Power Supply Backup
  700
- RTC Power Supply Backup
  703
- Mode Transitions
  705
- Figure 17.4 Mode Transition Diagram
  705
- STATUS Pin Change Timing
  706
  - In Reset
    706
  - In Sleep
    706
  - Figure 17.5 Status Pins Output from Sleep to Interrupt
    706
Section 18 Timer Unit (TMU)

707
- Features
  707
- Figure 18.1 Block Diagram of TMU
  708
- Input/Output Pins
  709
- Table 18.1 Pin Configuration
  709
- Register Descriptions
  710
- Operation
  719
- Interrupts
  724
- Table 18.4 TMU Interrupt Sources
  724
- Usage Notes
  725
  - Register Writes
    725
  - Reading from TCNT
    725
  - Reset RTC Frequency Divider Circuit
    725
  - External Clock Frequency
    725
Section 19 Compare Match Timer (CMT)

727
Section 20 Realtime Clock (RTC)

757
- Figure 20.1 Block Diagram of RTC
  758
  - Input/Output Pins
    759
  - Table 20.1 RTC Pins
    759
  - Table 20.2 RTC Registers
    760
  - Table 20.3 Register States of RTC in each Processing Mode
    761
  - Hz Counter (R64CNT)
    762
  - Minute Counter (RMINCNT)
    763
  - Day-Of-Week Counter (RWKCNT)
    764
  - Day Counter (RDAYCNT)
    765
  - Month Counter (RMONCNT)
    766
  - Second Alarm Register (RSECAR)
    767
  - Hour Alarm Register (RHRAR)
    768
  - Day Alarm Register (RDAYAR)
    769
  - Month Alarm Register (RMONAR)
    770
  - RTC Control Register 1 (RCR1)
    771
  - RTC Control Register 2 (RCR2)
    773
  - RTC Control Register (RCR3)
    776
- Operation
  777
- Interrupts
  780
- Usage Notes
  780
Section 21 Serial Communication Interface with FIFO (SCIF)

783
Section 22 Serial I/O with FIFO (SIOF)

847
Section 24 Multimedia Card Interface (MMCIF)

915
Section 25 Audio Codec Interface (HAC)

1005
- Features
  1005
- Input/Output Pins
  1006
- Figure 25.1 Block Diagram
  1006
- Table 25.1 Pin Configuration
  1006
- Register Descriptions
  1007
  - Table 25.2 Register Configuration
    1007
  - Table 25.3 Register States of HAC in each Processing Mode
    1007
  - Control and Status Register (HACCR)
    1008
  - Command/Status Address Register (HACCSAR)
    1010
  - Command/Status Data Register (HACCSDR)
    1012
  - PCM Left Channel Register (HACPCML)
    1013
  - PCM Right Channel Register (HACPCMR)
    1015
  - TX Interrupt Enable Register (HACTIER)
    1016
  - TX Status Register (HACTSR)
    1017
  - RX Interrupt Enable Register (HACRIER)
    1019
  - RX Status Register (HACRSR)
    1020
  - HAC Control Register (HACACR)
    1021
  - Figure 25.2 AC97 Frame Slot Structure
    1023
  - Table 25.4 AC97 Transmit Frame Structure
    1023
  - Operation
    1024
  - Table 25.5 AC97 Receive Frame Structure
    1024
  - Transmitter
    1025
  - Figure 25.3 Initialization Sequence
    1026
  - Figure 25.4 Sample Flowchart for Off-Chip Codec Register Write
    1027
  - Figure 25.5 Sample Flowchart for Off-Chip Codec Register Read (1)
    1028
  - Figure 25.6 Sample Flowchart for Off-Chip Codec Register Read (2)
    1029
  - Figure 25.7 Sample Flowchart for Off-Chip Codec Register Read (3)
    1030
  - Notes
    1031
Section 26 Serial Sound Interface (SSI) Module

1033
Section 27 NAND Flash Memory Controller (FLCTL)

1071
Section 28 General Purpose I/O (GPIO)

1105
- Table 28.1 Multiplexed Pins Controlled by Port Control Registers
  1106
  - Register Descriptions
    1110
  - Table 28.2 Register Configuration
    1110
  - Table 28.3 Register States of GPIO in each Processing Mode
    1112
  - Port a Control Register (PACR)
    1113
  - Port B Control Register (PBCR)
    1114
  - Port C Control Register (PCCR)
    1116
  - Port D Control Register (PDCR)
    1117
  - Port E Control Register (PECR)
    1119
  - Port F Control Register (PFCR)
    1120
  - Port G Control Register (PGCR)
    1122
  - Port H Control Register (PHCR)
    1124
  - Port J Control Register (PJCR)
    1125
  - Port K Control Register (PKCR)
    1127
  - Port L Control Register (PLCR)
    1129
  - Port M Control Register (PMCR)
    1130
  - Port a Data Register (PADR)
    1131
  - Port C Data Register (PCDR)
    1132
  - Port E Data Register (PEDR)
    1133
  - Port F Data Register (PFDR)
    1134
  - Port H Data Register (PHDR)
    1135
  - Port K Data Register (PKDR)
    1136
  - Port M Data Register (PMDR)
    1137
  - Port H Pull-Up Control Register (PHPUPR)
    1138
  - Port J Pull-Up Control Register (PJPUPR)
    1139
  - Port K Pull-Up Control Register (PKPUPR)
    1140
  - Port M Pull-Up Control Register (PMPUPR)
    1141
  - Input-Pin Pull-Up Control Register 1 (PPUPR1)
    1142
  - Input-Pin Pull-Up Control Register 2 (PPUPR2)
    1143
  - On-Chip Module Select Register (OMSELR)
    1144
  - Figure 28.1 Port Data Output Timing (Example of Port A)
    1147
- Usage Example
  1147
  - Figure 28.2 Port Data Input Timing (Example of Port A)
    1148
  - Port Input Function
    1148
  - On-Chip Module Function
    1149
Section 29 User Break Controller (UBC)

1151
- Figure 29.1 Block Diagram of UBC
  1152
- User Break Examples
  1178
- Usage Notes
  1182
Section 30 User Debugging Interface (H-UDI)

1185
- Features
  1185
- Figure 30.1 H-UDI Block Diagram
  1186
- Input/Output Pins
  1187
- Table 30.1 Pin Configuration
  1187
- Boundary Scan TAP Controllers (IDCODE, EXTEST, SAMPLE/PRELOAD, and BYPASS)
  1188
- Figure 30.2 Sequence for Switching from Boundary-Scan TAP Controller to H-UDI
  1189
- Table 30.2 Commands Supported by Boundary-Scan TAP Controller
  1189
- Register Descriptions
  1190
  - Table 30.3 Register Configuration (1)
    1190
  - Table 30.4 Register Configuration (2)
    1190
  - Table 30.5 Register Status in each Processing State
    1190
  - Instruction Register (SDIR)
    1191
  - Bypass Register (SDBPR)
    1192
  - Interrupt Source Register (SDINT)
    1192
  - Boundary Scan Register (SDBSR)
    1193
  - Table 30.6 SDBSR Configuration
    1193
- Operation
  1202
  - TAP Control
    1202
  - Figure 30.3 TAP Controller State Transitions
    1202
  - H-UDI Reset
    1203
  - H-UDI Interrupt
    1203
  - Figure 30.4 H-UDI Reset
    1203
- Usage Notes
  1204
Section 31 Electrical Characteristics

1205
Appendix

1267
- Figure B.1 Instruction Prefetch
  1269
  - B. Instruction Prefetching and Its Side Effects
    1269
  - C. Speculative Execution for Subroutine Return
    1270
  - D. Register Address Map
    1271
  - Figure E.1 Package Dimensions (449-Pin BGA)
    1305
  - F. Mode Pin Settings
    1306
  - Table F.1 Clock Operating Modes with External Pin Combination
    1306
  - Table F.2 Area 0 Memory Map and Bus Width
    1306
  - Table F.3 Endian
    1306
  - Table F.4 PCI Mode
    1307
  - Table F.5 Clock Input
    1307
  - Table F.6 Mode Control
    1307
  - G. Pin Functions
    1308
  - Table G.1 Pin States in Reset, Power-Down State, and Bus-Released State
    1308
  - G.2 Handling of Unused Pins
    1317
  - Table G.2 Treatment of Unused Pins
    1317
  - Figure H.1 Sequence of Turning on and off Power Supply
    1325
  - I. Version Registers (PVR, PRR)
    1326
  - Table I.1 Register Configuration
    1326
  - Table J.1 SH7780 Product Lineup
    1327
- J. Part Number List
  1327
Index

1329

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Renesas SH7780 Series Microcontrollers Manuals

Renesas SH7780 Series Hardware Manual (1340 pages)

Table of Contents

Section 1 Overview

Section 2 Programming Model

Section 3 Instruction Set

Section 4 Pipelining

Section 5 Exception Handling

Section 6 Floating-Point Unit (FPU)

Section 7 Memory Management Unit (MMU)

Section 8 Caches

Section 9 L Memory

Section 10 Interrupt Controller (INTC)

Section 11 Local Bus State Controller (LBSC)

Section 12 DDR-SDRAM Interface (DDRIF)

Section 13 PCI Controller (PCIC)

Section 14 Direct Memory Access Controller (DMAC)

Section 15 Clock Pulse Generator (CPG)

Section 16 Watchdog Timer and Reset

Section 17 Power-Down Mode

Section 18 Timer Unit (TMU)

Section 19 Compare Match Timer (CMT)

Section 20 Realtime Clock (RTC)

Section 21 Serial Communication Interface with FIFO (SCIF)

Section 22 Serial I/O with FIFO (SIOF)

Section 24 Multimedia Card Interface (MMCIF)

Section 25 Audio Codec Interface (HAC)

Section 26 Serial Sound Interface (SSI) Module

Section 27 NAND Flash Memory Controller (FLCTL)

Section 28 General Purpose I/O (GPIO)

Section 29 User Break Controller (UBC)

Section 30 User Debugging Interface (H-UDI)

Section 31 Electrical Characteristics

Appendix

Index

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