Output Timing - Renesas H8/3067 Series User Manual

Renesas 16-bit single-chip microcomputer
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11.3.2

Output Timing

If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output
when the selected compare match event occurs. Figure 11.3 shows the timing of these operations
for the case of normal output in groups 2 and 3, triggered by compare match A.
φ
TCNT
GRA
Compare
match A signal
NDRB
PBDR
TP to TP
8
15
Figure 11.3 Timing of Transfer of Next Data Register Contents and Output (Example)
Section 11 Programmable Timing Pattern Controller (TPC)
N
N + 1
N
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Rev. 4.00 Jan 26, 2006 page 453 of 938
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REJ09B0276-0400

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