External Address Area; Chip Select Signals; Figure 6.2 Csn Signal Output Polarity And Output Timing - Renesas H8S/2437 Hardware Manual

6.4.2

External Address Area

The initial condition of the external address space is normal extended 3-state access space. The
space outside the on-chip ROM, on-chip RAM, internal I/O register, and their reserved areas are
available as the external address spaces. When the RAME bit in SYSCR is set to 1, the on-chip
RAM and its reserved area are enabled. However if the RAME bit is cleared to 0, the on-chip
RAM and its reserved area are ignored. When the RAME bit is 0, H'FF0000 to H'FF9FFF of the
on-chip RAM and its reserved area, becomes an external address area.
6.4.3

Chip Select Signals

This LSI can output chip select signals (CS1 to CS3) for areas 0 to 3 respectively. The CS1 to CS3
signal outputs low or high level when the corresponding external space area is accessed. The chip
select signal's output polarity can be controlled by the PNCCSn bit in BCRAn. Figure 6.2 shows
an example of CS1 to CS3 signal's output polarity and output timing.
Selection of CS1 to CS3 signal output and I/O port input/output is set by the port function control
register (PFCR) bit for the port corresponding to the CS1 to CS3 pins. In external extended mode,
all of the CS1 to CS3 pins function as I/O ports after a reset. Therefore the corresponding PFCR
bits should be set to 1 when outputting signals CS1 to CS3. For details, refer to section 7, I/O
Ports.
Address bus
(PNCCS = 0)
(PNCCS = 1)
Note: n = 1 to 3
Figure 6.2 CS
Rev. 1.00, 09/03, page 100 of 704
T 1
External address of area n
CSn n n n Signal Output Polarity and Output Timing
CS CS
Bus cycle
T 2 T 3