Renesas SH7781 Manuals

Manuals and User Guides for Renesas SH7781. We have 1 Renesas SH7781 manual available for free PDF download: Hardware Manual

Renesas SH7781 Hardware Manual (1692 pages)

32-Bit RISC Microcomputer SuperH RISC Engine Family SH7780 Series

Brand: Renesas | Category: Computer Hardware | Size: 8.11 MB

Table of Contents
9
Section 1 Overview

31
- Features of the SH7785
  31
- Block Diagram
  43
- Pin Arrangement Table
  44
- Pin Arrangement
  52
- Physical Memory Address Map
  54
Section 2 Programming Model

55
- Data Formats
  55
  - Privileged Mode and Banks
    56
  - Register Descriptions
    56
  - General Registers
    60
  - Floating-Point Registers
    61
  - Control Registers
    63
  - System Registers
    65
- Memory-Mapped Registers
  69
- Data Formats in Registers
  70
- Data Formats in Memory
  70
- Processing States
  71
  - Usage Notes
    73
  - Notes on Self-Modifying Code
    73
Section 3 Instruction Set

75
- Execution Environment
  75
- Addressing Modes
  77
- Instruction Set
  82
Section 4 Pipelining

95
- Pipelines
  95
- Parallel-Executability
  106
- Issue Rates and Execution Cycles
  109
Section 5 Exception Handling

119
- Summary of Exception Handling
  119
- Exception Handling Functions
  125
  - Exception Handling Flow
    125
  - Exception Handling Vector Addresses
    125
- Exception Types and Priorities
  126
- Exception Flow
  128
- Rej09B0261
  130
  - Exception Source Acceptance
    130
  - Exception Requests and BL Bit
    131
  - Return from Exception Handling
    131
- Description of Exceptions
  132
  - Resets
    132
  - General Exceptions
    134
  - Interrupts
    150
  - Priority Order with Multiple Exceptions
    151
  - Usage Notes
    153
Section 6 Floating-Point Unit (FPU)

155
- Features
  155
- Data Formats
  156
- Floating-Point Format
  156
- Non-Numbers (Nan)
  159
- Denormalized Numbers
  160
  - Floating-Point Registers
    161
  - Register Descriptions
    161
- Floating-Point Status/Control Register (FPSCR)
  163
- Floating-Point Communication Register (FPUL)
  166
- Rounding
  167
- Floating-Point Exceptions
  168
- Graphics Support Functions
  170
  - Geometric Operation Instructions
    170
  - Pair Single-Precision Data Transfer
    171
Section 7 Memory Management Unit (MMU)

173
- Overview of MMU
  174
- Address Spaces
  176
- Register Descriptions
  182
- Page Table Entry High Register (PTEH)
  183
- Page Table Entry Low Register (PTEL)
  184
- Translation Table Base Register (TTB)
  185
- MMU Control Register (MMUCR)
  186
- TLB Exception Address Register (TEA)
  186
- Page Table Entry Assistance Register (PTEA)
  189
- Physical Address Space Control Register (PASCR)
  190
- Instruction Re-Fetch Inhibit Control Register (IRMCR)
  192
- TLB Functions (TLB Compatible Mode; MMUCR.ME = 0)
  194
  - Instruction TLB (ITLB) Configuration
    197
  - Address Translation Method
    197
- Unified TLB (UTLB) Configuration
  194
- TLB Functions (TLB Extended Mode; MMUCR.ME = 1)
  200
  - Unified TLB (UTLB) Configuration
    200
  - Instruction TLB (ITLB) Configuration
    203
  - Address Translation Method
    204
  - MMU Hardware Management
    207
  - MMU Software Management
    207
- MMU Functions
  207
  - MMU Instruction (LDTLB)
    208
  - Hardware ITLB Miss Handling
    210
  - Avoiding Synonym Problems
    211
  - Instruction TLB Multiple Hit Exception
    212
- MMU Exceptions
  212
- Memory-Mapped TLB Configuration
  220
  - ITLB Address Array
    221
  - ITLB Data Array (TLB Compatible Mode)
    222
  - ITLB Data Array (TLB Extended Mode)
    223
  - UTLB Address Array
    225
  - UTLB Data Array (TLB Compatible Mode)
    226
  - UTLB Data Array (TLB Extended Mode)
    227
- Bit Address Extended Mode
  229
- Bit Boot Function
  237
  - Initial Entries to PMB
    237
  - Notes on 32-Bit Boot
    237
  - Note on Using LDTLB Instruction
    239
  - Usage Notes
    239
Section 8 Caches

241
- Features
  241
- Register Descriptions
  245
- Cache Control Register (CCR)
  246
- Queue Address Control Register 0 (QACR0)
  248
- Queue Address Control Register 1 (QACR1)
  249
- On-Chip Memory Control Register (RAMCR)
  250
- Operand Cache Operation
  252
  - Read Operation
    252
  - Prefetch Operation
    253
  - Write Operation
    254
  - Write-Back Buffer
    255
  - Write-Through Buffer
    255
  - OC Two-Way Mode
    256
- Instruction Cache Operation
  257
  - Read Operation
    257
  - Prefetch Operation
    257
  - IC Two-Way Mode
    258
  - Instruction Cache Way Prediction Operation
    258
- Cache Operation Instruction
  259
  - Coherency between Cache and External Memory
    259
  - Prefetch Operation
    261
- Memory-Mapped Cache Configuration
  262
  - IC Address Array
    262
  - IC Data Array
    264
  - OC Address Array
    264
  - OC Data Array
    266
  - Memory-Mapped Cache Associative Write Operation
    267
- Store Queues
  268
  - SQ Configuration
    268
  - Writing to SQ
    268
  - Transfer to External Memory
    269
  - Determination of SQ Access Exception
    270
  - Reading from SQ
    270
  - Notes on Using 32-Bit Address Extended Mode
    271
Section 9 On-Chip Memory

273
- Features
  273
- Register Descriptions
  276
- On-Chip Memory Control Register (RAMCR)
  277
- OL Memory Transfer Source Address Register 0 (LSA0)
  278
- OL Memory Transfer Source Address Register 1 (LSA1)
  280
- OL Memory Transfer Destination Address Register 0 (LDA0)
  282
- OL Memory Transfer Destination Address Register 1 (LDA1)
  284
- Instruction Fetch Access from the CPU
  286
- Operand Access from the CPU and Access from the FPU
  286
- Operation
  286
- Access from the Superhyway Bus Master Module
  287
- OL Memory Block Transfer
  287
- On-Chip Memory Protective Functions
  290
  - Page Conflict
    291
  - Usage Notes
    291
  - Access Across Different
    291
  - On-Chip Memory Coherency
    291
- Note on Using 32-Bit Address Extended Mode
  292
- Sleep Mode
  292
Section 10 Interrupt Controller (INTC)

293
- Features
  293
- Interrupt Method
  296
- Interrupt Sources
  297
  - Input/Output Pins
    302
  - Register Descriptions
    303
  - External Interrupt Request Registers
    307
  - User Mode Interrupt Disable Function
    328
  - On-Chip Module Interrupt Priority Registers
    330
  - Individual On-Chip Module Interrupt Source Registers (INT2B0 to INT2B7)
    344
  - GPIO Interrupt Set Register (INT2GPIC)
    352
  - Interrupt Sources
    354
  - IRQ Interrupts
    354
  - NMI Interrupts
    354
  - IRL Interrupts
    355
  - On-Chip Peripheral Module Interrupts
    357
  - Priority of On-Chip Peripheral Module Interrupts
    358
  - Interrupt Exception Handling and Priority
    359
  - Interrupt Sequence
    367
  - Operation
    367
  - Interrupt Masking by MAI Bit
    369
  - Multiple Interrupts
    369
- Interrupt Response Time
  370
Section 11 Local Bus State Controller (LBSC)

377
- Features
  377
- Input/Output Pins
  380
- Overview of Areas
  384
- Space Divisions
  384
- Memory Bus Width
  387
- PCMCIA Support
  388
- Register Descriptions
  392
- Memory Address Map Select Register (MMSELR)
  394
- Bus Control Register (BCR)
  397
- Csn Bus Control Register (Csnbcr)
  401
- Csn Wait Control Register (Csnwcr)
  407
- Csn PCMCIA Control Register (Csnpcr)
  412
- Endian/Access Size and Data Alignment
  417
- Operation
  417
- Areas
  428
- SRAM Interface
  433
- Burst ROM Interface
  442
- PCMCIA Interface
  446
- MPX Interface
  457
- Byte Control SRAM Interface
  471
- Wait Cycles between Access Cycles
  476
- Bus Arbitration
  478
- Master Mode
  480
- Cooperation between Master and Slave
  481
- Power-Down Mode and Bus Arbitration
  481
- Slave Mode
  481
- Mode Pin Settings and General Input Output Port Settings about Data Bus Width
  482
- Pins Multiplexed with Other Modules Functions
  482
- Register Settings for Divided-Up Dackn Output
  482
Section 12 DDR2-SDRAM Interface (DBSC2)

487
- Features
  487
- Input/Output Pins
  490
- Data Alignment
  495
- Register Descriptions
  509
- DBSC2 Status Register (DBSTATE)
  512
- SDRAM Operation Enable Register (DBEN)
  513
- SDRAM Command Control Register (DBCMDCNT)
  514
- SDRAM Configuration Setting Register (DBCONF)
  516
- SDRAM Timing Register 0 (DBTR0)
  518
- SDRAM Timing Register 1 (DBTR1)
  522
- SDRAM Timing Register 2 (DBTR2)
  525
- SDRAM Refresh Control Register 0 (DBRFCNT0)
  529
- SDRAM Refresh Control Register 1 (DBRFCNT1)
  530
- SDRAM Refresh Control Register 2 (DBRFCNT2)
  532
- SDRAM Refresh Status Register (DBRFSTS)
  534
- DDRPAD Frequency Setting Register (DBFREQ)
  535
- DDRPAD DIC, ODT, OCD Setting Register (DBDICODTOCD)
  537
- SDRAM Mode Setting Register (DBMRCNT)
  540
- DBSC2 Operation
  542
Section 13 PCI Controller (PCIC)

581
- Features
  581
- Input/Output Pins
  584
- Register Descriptions
  587
- PCIC Enable Control Register (PCIECR)
  592
- Configuration Registers
  593
- PCI Local Registers
  620
- Operation
  660
- Supported PCI Commands
  660
- PCIC Initialization
  661
- Master Access
  662
- Target Access
  670
- Host Mode
  678
- Normal Mode
  681
- Power Management
  681
- PCI Local Bus Basic Interface
  683
Section 14 Direct Memory Access Controller (DMAC)

695
- Features
  695
- Input/Output Pins
  697
- Register Descriptions
  698
- DMA Source Address Registers 0 to 11 (SAR0 to SAR11)
  705
- DMA Destination Address Registers 0 to 11 (DAR0 to DAR11)
  707
- DMA Transfer Count Registers 0 to 11 (TCR0 to TCR11)
  709
- DMA Channel Control Registers 0 to 11 (CHCR0 to CHCR11)
  711
- DMA Operation Register 0, 1 (DMAOR0 and DMAOR1)
  719
- DMA Extended Resource Selectors 0 to 5 (DMARS0 to DMARS5)
  723
- DMA Transfer Requests
  731
- Operation
  731
- Channel Priority
  736
- DMA Transfer Types
  739
- DMA Transfer Flow
  747
- Repeat Mode Transfer
  749
- Reload Mode Transfer
  750
- DREQ Pin Sampling Timing
  751
- DMAC Interrupt Sources
  759
  - Stopping Modules and Changing Frequency
    760
  - Usage Notes
    760
  - Address Error
    760
  - NMI Interrupt
    760
  - Burst Mode Transfer
    760
  - Divided-Up DACK Output
    760
  - DACK/DREQ Setting
    761
Section 15 Clock Pulse Generator (CPG)

763
- Features
  763
- Input/Output Pins
  766
- Clock Operating Modes
  767
- Calculating the Frequency
  778
- How to Change the Frequency
  779
Section 16 Watchdog Timer and Reset (WDT)

789
- Features
  789
- Input/Output Pins
  791
- Register Descriptions
  792
- Watchdog Timer Stop Time Register (WDTST)
  793
- Watchdog Timer Control/Status Register (WDTCSR)
  794
- Watchdog Timer Base Stop Time Register (WDTBST)
  796
- Watchdog Timer Counter (WDTCNT)
  797
- Watchdog Timer Base Counter (WDTBCNT)
  798
- Operation
  799
- Reset Request
  799
- Using Interval Timer Mode
  801
- Using Watchdog Timer Mode
  801
- Time until WDT Counters Overflow
  802
- Clearing WDT Counters
  803
- Status Pin Change Timing During Reset
  804
Section 17 Power-Down Mode

811
- Features
  811
- Types of Power-Down Modes
  811
  - Input/Output Pins
    813
  - Register Descriptions
    813
- Sleep Control Register (SLPCR)
  815
- Standby Control Register 0 (MSTPCR0)
  816
- Standby Control Register 1 (MSTPCR1)
  819
- Standby Display Register (MSTPMR)
  821
- Releasing Sleep Mode
  823
- Transition to Sleep Mode
  823
- Deep Sleep Mode
  824
  - Transition to Deep Sleep Mode
    824
  - Releasing Deep Sleep Mode
    825
- Module Standby Functions
  826
  - Transition to Module Standby Mode
    826
  - Releasing Module Standby Functions
    826
- DDR-SDRAM Power Supply Backup
  827
- Timing of the Changes on the STATUS Pins
  827
  - Reset
    827
  - Releasing Sleep Mode
    827
Section 18 Timer Unit (TMU)

829
- Features
  829
- Input/Output Pins
  831
- Register Descriptions
  832
- Timer Start Registers (Tstrn) (N = 0, 1)
  834
- Timer Constant Registers (Tcorn) (N = 0 to 5)
  836
- Timer Counters (Tcntn) (N = 0 to 5)
  836
- Timer Control Registers (Tcrn) (N = 0 to 5)
  837
- Input Capture Register 2 (TCPR2)
  839
- Counter Operation
  840
- Input Capture Function
  843
- Interrupts
  844
- External Clock Frequency
  845
- Reading from TCNT
  845
- Register Writes
  845
- Usage Notes
  845
Section 19 Display Unit (DU)

847
Section 20 Graphics Data Translation Accelerator (GDTA)

999
- Features
  999
- GDTA Address Space
  1003
- GDTA Operation
  1043
  - Explanation of CL Operation
    1043
  - Explanation of MC Operation
    1049
- Interrupt Processing
  1059
- Data Alignment
  1059
  - Regarding Module Stop
    1061
  - Usage Notes
    1061
  - Regarding Deep Sleep Modes
    1061
  - Regarding Frequency Changes
    1062
Section 21 Serial Communication Interface with FIFO (SCIF)

1063
- Features
  1063
- Input/Output Pins
  1069
- Register Descriptions
  1070
  - Receive Shift Register (SCRSR)
    1076
  - Receive FIFO Data Register (SCFRDR)
    1076
  - Transmit Shift Register (SCTSR)
    1077
  - Transmit FIFO Data Register (SCFTDR)
    1077
  - Serial Mode Register (SCSMR)
    1078
  - Serial Control Register (SCSCR)
    1081
  - Serial Status Register N (SCFSR)
    1085
  - Bit Rate Register N (SCBRR)
    1091
  - FIFO Control Register N (SCFCR)
    1092
  - Transmit FIFO Data Count Register N (SCTFDR)
    1094
  - Receive FIFO Data Count Register N (SCRFDR)
    1095
  - Serial Port Register N (SCSPTR)
    1096
  - Line Status Register N (SCLSR)
    1099
  - Serial Error Register N (SCRER)
    1100
  - Overview
    1101
- Operation
  1101
  - Operation in Asynchronous Mode
    1104
  - Operation in Clocked Synchronous Mode
    1115
- SCIF Interrupt Sources and the DMAC
  1124
- Usage Notes
  1126
Section 22 Serial I/O with FIFO (SIOF)

1129
- Features
  1129
- Input/Output Pins
  1131
- Register Descriptions
  1132
  - Mode Register (SIMDR)
    1134
  - Control Register (SICTR)
    1136
  - Transmit Data Register (SITDR)
    1138
  - Receive Data Register (SIRDR)
    1139
  - Transmit Control Data Register (SITCR)
    1140
  - Receive Control Data Register (SIRCR)
    1141
  - Status Register (SISTR)
    1142
  - Interrupt Enable Register (SIIER)
    1148
  - FIFO Control Register (SIFCTR)
    1150
  - Clock Select Register (SISCR)
    1152
  - Transmit Data Assign Register (SITDAR)
    1153
  - Receive Data Assign Register (SIRDAR)
    1155
  - Control Data Assign Register (SICDAR)
    1156
  - Serial Clocks
    1158
- Operation
  1158
  - Serial Timing
    1159
  - Transfer Data Format
    1161
  - Register Allocation of Transfer Data
    1163
  - Control Data Interface
    1165
  - Fifo
    1167
  - Transmit and Receive Procedures
    1169
  - Interrupts
    1174
  - Transmit and Receive Timing
    1176
Section 23 Serial Peripheral Interface (HSPI)

1181
- Features
  1181
- Input/Output Pins
  1183
- Register Descriptions
  1183
- Control Register (SPCR)
  1185
- Status Register (SPSR)
  1188
- System Control Register (SPSCR)
  1191
- Transmit Buffer Register (SPTBR)
  1193
- Receive Buffer Register (SPRBR)
  1194
- Operation Overview with FIFO Mode Disabled
  1195
- Operation with FIFO Mode Enabled
  1196
- Timing Diagrams
  1197
- Clock Polarity and Transmit Control
  1199
- HSPI Software Reset
  1199
- Transmit and Receive Routines
  1199
- Flags and Interrupt Timing
  1200
- Low-Power Consumption and Clock Synchronization
  1200
Section 24 Multimedia Card Interface (MMCIF)

1201
- Features
  1201
- Input/Output Pins
  1202
- Register Descriptions
  1203
- Command Registers 0 to 5 (CMDR0 to CMDR5)
  1207
- Command Start Register (CMDSTRT)
  1208
- Operation Control Register (OPCR)
  1209
- Card Status Register (CSTR)
  1211
- Interrupt Control Registers 0 to 2 (INTCR0 to INTCR2)
  1213
- Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2)
  1217
- Transfer Clock Control Register (CLKON)
  1223
- Command Timeout Control Register (CTOCR)
  1224
- Transfer Byte Number Count Register (TBCR)
  1225
- Mode Register (MODER)
  1226
- Command Type Register (CMDTYR)
  1227
- Response Type Register (RSPTYR)
  1228
- Transfer Block Number Counter (TBNCR)
  1232
- Response Registers 0 to 16, D (RSPR0 to RSPR16, RSPRD)
  1233
- Data Timeout Register (DTOUTR)
  1235
- Data Register (DR)
  1236
- FIFO Pointer Clear Register (FIFOCLR)
  1237
- DMA Control Register (DMACR)
  1238
- Operations in MMC Mode
  1239
- MMCIF Interrupt Sources
  1269
  - Operation in Read Sequence
    1270
  - Operations When Using DMA
    1270
  - Operation in Write Sequence
    1280
- Register Accesses with Little Endian Specification
  1291
Section 25 Audio Codec Interface (HAC)

1293
- Features
  1293
- Input/Output Pins
  1295
- Register Descriptions
  1296
- Control and Status Register (HACCR)
  1299
- Command/Status Address Register (HACCSAR)
  1301
- Command/Status Data Register (HACCSDR)
  1303
- PCM Left Channel Register (HACPCML)
  1305
- PCM Right Channel Register (HACPCMR)
  1307
- TX Interrupt Enable Register (HACTIER)
  1308
- TX Status Register (HACTSR)
  1309
- RX Interrupt Enable Register (HACRIER)
  1311
- RX Status Register (HACRSR)
  1312
- HAC Control Register (HACACR)
  1314
- AC 97 Frame Slot Structure
  1316
  - Receiver
    1318
  - Operation
    1318
  - Transmitter
    1318
  - Interrupts
    1319
  - Initialization Sequence
    1320
  - Power-Down Mode
    1325
  - Notes
    1325
  - Reference
    1325
Section 26 Serial Sound Interface (SSI) Module

1327
- Features
  1327
- Input/Output Pins
  1329
- Register Descriptions
  1330
- Control Register (SSICR)
  1331
- Status Register (SSISR)
  1338
- Receive Data Register (SSIRDR)
  1343
- Transmit Data Register (SSITDR)
  1343
- Bus Format
  1344
- Operation
  1344
- Non-Compressed Modes
  1345
- Compressed Modes
  1354
- Operation Modes
  1357
- Transmit Operation
  1358
- Receive Operation
  1361
- Serial Clock Control
  1364
- Usage Note
  1365
Section 27 NAND Flash Memory Controller (FLCTL)

1367
- Features
  1367
- Input/Output Pins
  1370
- Register Descriptions
  1372
- Common Control Register (FLCMNCR)
  1374
- Command Control Register (FLCMDCR)
  1376
- Command Code Register (FLCMCDR)
  1378
- Address Register (FLADR)
  1379
- Address Register 2 (FLADR2)
  1381
- Data Counter Register (FLDTCNTR)
  1382
- Data Register (FLDATAR)
  1383
- Interrupt DMA Control Register (FLINTDMACR)
  1384
- Ready Busy Timeout Setting Register (FLBSYTMR)
  1389
- Ready Busy Timeout Counter (FLBSYCNT)
  1390
- Data FIFO Register (FLDTFIFO)
  1391
- Control Code FIFO Register (FLECFIFO)
  1392
- Transfer Control Register (FLTRCR)
  1393
- Command Access Mode
  1394
- Operating Modes
  1394
- Operation
  1394
- Sector Access Mode
  1398
- Status Read
  1401
- Example of Register Setting
  1403
- DMA Transfer Settings
  1406
- Interrupt Processing
  1406
Section 28 General Purpose I/O Ports (GPIO)

1407
- Features
  1407
- Register Descriptions
  1412
- Port a Control Register (PACR)
  1416
- Port B Control Register (PBCR)
  1419
- Port C Control Register (PCCR)
  1421
- Port D Control Register (PDCR)
  1423
- Port E Control Register (PECR)
  1425
- Port F Control Register (PFCR)
  1427
- Port G Control Register (PGCR)
  1429
- Port H Control Register (PHCR)
  1431
- Port J Control Register (PJCR)
  1433
- Port K Control Register (PKCR)
  1435
- Port L Control Register (PLCR)
  1437
- Port M Control Register (PMCR)
  1439
- Port N Control Register (PNCR)
  1440
- Port P Control Register (PPCR)
  1442
- Port Q Control Register (PQCR)
  1444
- Port R Control Register (PRCR)
  1446
- Port a Data Register (PADR)
  1448
- Port B Data Register (PBDR)
  1449
- Port C Data Register (PCDR)
  1450
- Port D Data Register (PDDR)
  1451
- Port E Data Register (PEDR)
  1452
- Port F Data Register (PFDR)
  1453
- Port G Data Register (PGDR)
  1454
- Port H Data Register (PHDR)
  1455
- Port J Data Register (PJDR)
  1456
- Port K Data Register (PKDR)
  1457
- Port L Data Register (PLDR)
  1458
- Port M Data Register (PMDR)
  1459
- Port N Data Register (PNDR)
  1460
- Port P Data Register (PPDR)
  1461
- Port Q Data Register (PQDR)
  1462
- Port R Data Register (PRDR)
  1463
- Port E Pull-Up Control Register (PEPUPR)
  1464
- Port H Pull-Up Control Register (PHPUPR)
  1465
- Port J Pull-Up Control Register (PJPUPR)
  1466
- Port K Pull-Up Control Register (PKPUPR)
  1467
- Port L Pull-Up Control Register (PLPUPR)
  1468
- Port M Pull-Up Control Register (PMPUPR)
  1469
- Port N Pull-Up Control Register (PNPUPR)
  1470
- Input-Pin Pull-Up Control Register 1 (PPUPR1)
  1471
- Input-Pin Pull-Up Control Register 2 (PPUPR2)
  1471
- Peripheral Module Select Register 1 (P1MSELR)
  1473
- Peripheral Module Select Register 2 (P2MSELR)
  1477
- Usage Example
  1479
  - Port Output Function
    1479
  - Port Input Function
    1480
  - Peripheral Module Function
    1481
Section 29 User Break Controller (UBC)

1483
- Features
  1483
- Register Descriptions
  1485
- Match Condition Setting Registers 0 and 1 (CBR0 and CBR1)
  1487
- Match Operation Setting Registers 0 and 1 (CRR0 and CRR1)
  1493
- Match Address Setting Registers 0 and 1 (CAR0 and CAR1)
  1495
- Match Address Mask Setting Registers 0 and 1 (CAMR0 and CAMR1)
  1496
- Match Data Setting Register 1 (CDR1)
  1498
- Match Data Mask Setting Register 1 (CDMR1)
  1499
- Execution Count Break Register 1 (CETR1)
  1500
- Channel Match Flag Register (CCMFR)
  1501
- Break Control Register (CBCR)
  1502
- Definition of Words Related to Accesses
  1503
- Operation Description
  1503
- User Break Operation Sequence
  1504
- Instruction Fetch Cycle Break
  1505
- Operand Access Cycle Break
  1506
- Sequential Break
  1507
- Program Counter Value to be Saved
  1509
- User Break Debugging Support Function
  1510
- User Break Examples
  1511
- Usage Notes
  1515
Section 30 User Debugging Interface (H-UDI)

1517
- Features
  1517
- Input/Output Pins
  1519
- Register Description
  1521
  - Instruction Register (SDIR)
    1522
  - Interrupt Source Register (SDINT)
    1522
  - Bypass Register (SDBPR)
    1523
  - Boundary Scan Register (SDBSR)
    1523
  - Boundary-Scan TAP Controller (IDCODE, EXTEST, SAMPLE/PRELOAD and BYPASS)
    1533
- Operation
  1533
  - TAP Control
    1535
  - H-UDI Reset
    1536
  - H-UDI Interrupt
    1537
  - Usage Notes
    1537
Section 31 Register List

1539
- Register Address List
  1539
- States of the Registers in the Individual Operating Modes
  1563
Section 32 Electrical Characteristics

1591
- Absolute Maximum Ratings
  1591
- DC Characteristics
  1592
- AC Characteristics
  1597
  - Clock and Control Signal Timing
    1598
  - Control Signal Timing
    1602
  - Bus Timing
    1604
  - Electrical Characteristics
    1612
  - DBSC2 Signal Timing
    1622
  - INTC Module Signal Timing
    1627
  - PCIC Module Signal Timing
    1629
  - DMAC Module Signal Timing
    1631
  - TMU Module Signal Timing
    1632
  - SCIF Module Signal Timing
    1633
  - H-UDI Module Signal Timing
    1635
  - GPIO Signal Timing
    1637
  - HSPI Module Signal Timing
    1638
  - SIOF Module Signal Timing
    1639
  - MMCIF Module Signal Timing
    1643
  - HAC Interface Module Signal Timing
    1644
  - SSI Interface Module Signal Timing
    1646
  - FLCTL Module Signal Timing
    1648
  - Display Unit Signal Timing
    1652
- AC Characteristic Test Conditions
  1655
Appendix

1657
- A. Package Dimensions
  1657
- B. Mode Pin Settings
  1658
- C. Pin Functions
  1661
- C.1 Pin States
  1661
- C.2 Handling of Unused Pins
  1672
- D. Turning on and off Power Supply
  1683
- D.1 Turning on and off between each Power Supply Series
  1683
- D.2 Power-On and Power-Off Sequences for Power Supplies with Different Potentials in DDR2-SDRAM Power Supply Backup Mode
  1684
- D.3 Turning on and off between the same Power Supply Series
  1685
- E. Version Registers (PVR, PRR)
  1686
- F. Product Lineup
  1687

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Renesas SH7781 Manuals

Renesas SH7781 Hardware Manual (1692 pages)

Table of Contents

Section 1 Overview

Section 2 Programming Model

Section 3 Instruction Set

Section 4 Pipelining

Section 5 Exception Handling

Section 6 Floating-Point Unit (FPU)

Section 7 Memory Management Unit (MMU)

Section 8 Caches

Section 9 On-Chip Memory

Section 10 Interrupt Controller (INTC)

Section 11 Local Bus State Controller (LBSC)

Section 12 DDR2-SDRAM Interface (DBSC2)

Section 13 PCI Controller (PCIC)

Section 14 Direct Memory Access Controller (DMAC)

Section 15 Clock Pulse Generator (CPG)

Section 16 Watchdog Timer and Reset (WDT)

Section 17 Power-Down Mode

Section 18 Timer Unit (TMU)

Section 19 Display Unit (DU)

Section 20 Graphics Data Translation Accelerator (GDTA)

Section 21 Serial Communication Interface with FIFO (SCIF)

Section 22 Serial I/O with FIFO (SIOF)

Section 23 Serial Peripheral Interface (HSPI)

Section 24 Multimedia Card Interface (MMCIF)

Section 25 Audio Codec Interface (HAC)

Section 26 Serial Sound Interface (SSI) Module

Section 27 NAND Flash Memory Controller (FLCTL)

Section 28 General Purpose I/O Ports (GPIO)

Section 29 User Break Controller (UBC)

Section 30 User Debugging Interface (H-UDI)

Section 31 Register List

Section 32 Electrical Characteristics

Appendix

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