Timer Waveform Control Register (Twcr); Bus Master Interface - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.3.29

Timer Waveform Control Register (TWCR)

TWCR is an 8-bit readable/writable register that controls the waveform when synchronous counter clearing occurs in
TCNT_3 and TCNT_4 in complementary PWM mode and specifies whether to clear the counters at TGRA_3 compare
match. The CCE bit and WRE bit in TWCR must be modified only while TCNT stops.
Bit Bit Name
7 CCE
6 to 1 —
0 WRE
Note: Do not set to 1 when complementary PWM mode 1 is not selected.
*
10.3.30

Bus Master Interface

The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer cycle buffer register (TCBR),
timer dead time data register (TDDR), timer cycle data register (TCDR), timer A/D converter start request control
register (TADCR), timer A/D converter start request cycle set registers (TADCOR), and timer A/D converter start
request cycle set buffer registers (TADCOBR) are 16-bit registers. 16-bit read/writes is possible. 8-bit read/write is not
possible. Always access in 16-bit units.
All registers other than the above registers are 8-bit registers. 8-bit read/writes is possible. 16-bit read/writes is not
possible. Always access in 8-bit units.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit:
7 6
CCE -
Initial value:
0* 0
R/W:
R/(W) R
Initial
Value R/W Description
0* R/(W) Compare Match Clear Enable
Specifies whether to clear counters at TGRA_3 compare match in
complementary PWM mode.
0: Does not clear counters at TGRA_3 compare match
1: Clears counters at TGRA_3 compare match
[Setting condition]
• When 1 is written to CCE after reading CCE = 0
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0 R/(W) Initial Output Suppression Enable
Selects the waveform output when synchronous counter clearing occurs in
complementary PWM mode. The initial output is suppressed only when
synchronous clearing occurs within the Tb interval at the trough in
complementary PWM mode. When synchronous clearing occurs outside this
interval, the initial value specified in TOCR is output regardless of the WRE bit
setting. The initial value is also output when synchronous clearing occurs in the
Tb interval at the trough immediately after TCNT_3 and TCNT_4 start operation.
For the Tb interval at the trough in complementary PWM mode, see Figure
10.40.
0: Outputs the initial value specified in TOCR
1: Suppresses initial output
[Setting condition]
• When 1 is written to WRE after reading WRE = 0
5 4 3 2 1
- - - - -
0 0 0 0 0
R R R R R
10. Multi-Function Timer Pulse Unit 2
0
WRE
0
R/(W)
10-60