Figure 12.4 Continuous Access For Normal Space 1 Bus Width = 16 Bits, Longword Access, Csnwcr.wn Bit = 0 (Access Wait = 0, Cycle Wait = 0) - Renesas HD6417641 Hardware Manual

Section 12 Bus State Controller (BSC)
It is necessary to output the data that has been read using RD when a buffer is established in the
data bus. The RD/WR signal is in a read state (high output) when no access has been carried out.
Therefore, care must be taken when controlling the external data buffer, to avoid collision.
Figures 12.4 and 12.5 show the basic timings of normal space accesses. If the WM bit in
CSnWCR is cleared to 0, a Tnop cycle is inserted after the CSn space access to evaluate the
external wait (figure 12.4). If the WM bit in CSnWCR is set to 1, external waits are ignored and
no Tnop cycle is inserted (figure 12.5).
T1 T2 Tnop T1 T2
CKIO
A25 to A0
CSn
RD/WR
RD
Read
D15 to D0
WEn
Write
D15 to D0
BS
DACKn *
WAIT
Note: * The waveform for DACKn is when active low is specified.
Figure 12.4 Continuous Access for Normal Space 1
Bus Width = 16 Bits, Longword Access, CSnWCR.WN Bit = 0
(Access Wait = 0, Cycle Wait = 0)
Rev. 4.00 Sep. 14, 2005 Page 325 of 982
REJ09B0023-0400