Riicnbrl - I²C Bus Bit Rate Low-Level Register - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.3.12 RIICnBRL — I²C Bus Bit Rate Low-Level Register
Access: RIICnBRL is a 32-bit readable/writable register.
RIICnBRLL and RIICnBRLH are 16-bit readable/writable registers.
RIICnBRLLL, RIICnBRLLH, RIICnBRLHL, and RIICnBRLHH are 8-bit readable/writable registers.
Address: RIICnBRL: <RIICn_base> + 0034
RIICnBRLL: <RIICn_base> + 0034
RIICnBRLLL: <RIICn_base> + 0034
RIICnBRLHH: <RIICn_base> + 0037
Initial Value: 0000 00FF
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 18.18
Bit Position
31 to 8
7 to 5
4 to 0
The RIICnBRL register is a 5-bit register that is used to set the width at low level for the SCL clock.
It also works to generate the data setup time for automatic SCL low-hold operation (see Section
18.10, Automatically Low-Hold Function for SCL); when the RIIC is used only in slave mode, this
register needs to be set to a value equal to or longer than the data setup time*
RIICnBRL counts the low-level period with the internal reference clock source (IICφ) specified by the
RIICnMR1.CKS[2:0] bits.
Note 1.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
, RIICnBRLH: <RIICn_base> + 0036
H
, RIICnBRLLH: <RIICn_base> + 0035
H
H
This register is initialized by any reset.
H
28 27 26 25
— — —
0 0 0
R R R
12 11 10
— — —
0 0 0
R R R
RIICnBRL register contents
Bit Name Function
― Reserved
These bits are read as 0. The write value should be 0.
— Reserved
These bits are read as 1. The write value should be 1.
BRL[4:0] Bit Rate Low-Level Period
Low-level period of SCL clock
Data setup time (t )
SU: DAT
250 [ns] (0 to 100 [kbps]: standard mode (Sm))
100 [ns] (0 to 400 [kbps]: fast mode (Fm))
H
, RIICnBRLHL: <RIICn_base> + 0036
H
24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
— — — —
0 0 1 1
R R R R
18. I²C Bus Interface
H
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
— BRL[4:0]
1 1 1 1
R R/W R/W R/W
1
.
,
17 16
— —
0 0
R R
1 0
1 1
R/W R/W
18-37