Figure 6.7 Bus Timing For 16-Bit, 2-State Access Space (Even Byte Access) - Renesas H8S/2158 User Manual

16-Bit, 2-State Access Space: Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states cannot be
inserted.
CS256 (CS256E = 1)
CPCS1 (CPCSE = 1 and CFE = 0)
AS/IOS * (IOSE = 0)
Read
Write
Note: * For external address space access, this signal is not output when the 256-kbyte expansion area
is accessed with CS256E = 1 and when the CP/CF expansion area is accessed with CPCSE = 1.

Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)

φ
Address bus
AS/IOS (IOSE = 1)
RD
D15 to D8
D7 to D0
HWR
LWR
D15 to D8
D7 to D0
Bus cycle
T T
1 2
Valid
Invalid
High level
Valid
Undefined
Rev. 3.00 Jan 25, 2006 page 127 of 872
Section 6 Bus Controller
REJ09B0286-0300