Figure 9.33 Output Compare Output Timing; Figure 9.34 Input Capture Input Signal Timing - Renesas H8SX/1520 Series Hardware Manual

(2)
Output Compare Output Timing
A compare match signal is generated in the final state in which TCNT and TGR match (the point
at which the count value matched by TCNT is updated). When a compare match signal is
generated, the output value set in TIOR is output at the output compare output pin (TIOC pin).
After a match between TCNT and TGR, the compare match signal is not generated until the
TCNT input clock is generated.
Figure 9.33 shows output compare output timing.
(3)
Input Capture Signal Timing
Figure 9.34 shows input capture signal timing.
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Pφ
TCNT input
clock
TCNT
TGR
Compare match
signal
TIOC pin

Figure 9.33 Output Compare Output Timing

Pφ
Input capture
input
Input capture
signal
TCNT
TGR

Figure 9.34 Input Capture Input Signal Timing

N
N
N + 1
N
N
Section 9 16-Bit Timer Pulse Unit (TPU)
N + 1
N + 2
N + 2
Rev. 3.00 Mar. 14, 2006 Page 331 of 804
REJ09B0104-0300