Figure 10.32 Output Compare Output Timing; Figure 10.33 Input Capture Input Signal Timing - Renesas H8S/2368 Series Hardware Manual

φ
TCNT
input clock
TCNT
TGR
Compare
match signal
TIOC pin
Input Capture Signal Timing: Figure 10.33 shows input capture signal timing.
φ
Input capture
input
Input capture
signal
TCNT
TGR
Timing for Counter Clearing by Compare Match/Input Capture: Figure 10.34 shows the
timing when counter clearing by compare match occurrence is specified, and figure 10.35 shows
the timing when counter clearing by input capture occurrence is specified.
N
N

Figure 10.32 Output Compare Output Timing

N

Figure 10.33 Input Capture Input Signal Timing

N + 1
N + 1 N + 2
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Rev. 2.00, 05/03, page 439 of 820
N + 2