Figure 9.33 Output Compare Output Timing; Figure 9.34 Input Capture Input Signal Timing - Renesas H8SX/1500 Series Hardware Manual

(2)
Output Compare Output Timing
A compare match signal is generated in the final state in which TCNT and TGR match (the point
at which the count value matched by TCNT is updated). When a compare match signal is
generated, the output value set in TIOR is output at the output compare output pin (TIOC pin).
After a match between TCNT and TGR, the compare match signal is not generated until the
TCNT input clock is generated.
Figure 9.33 shows output compare output timing.
Pφ
TCNT input
clock
TCNT
TGR
Compare match
signal
TIOC pin
(3)
Input Capture Signal Timing
Figure 9.34 shows input capture signal timing.
Pφ
Input capture
input
Input capture
signal
TCNT
TGR
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Figure 9.33 Output Compare Output Timing

N

Figure 9.34 Input Capture Input Signal Timing

Section 9 16-Bit Timer Pulse Unit (TPU)
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