Timing Of Timer Output At Compare Match; Timing Of Counter Clear By Compare Match - Renesas H8SX/1650 Hardware Manual

Section 11 8-Bit Timers (TMR)
P
TCNT
TCOR
Compare match
signal
CMF
Figure 11.7 Timing of CMF Setting at Compare Match
11.5.3

Timing of Timer Output at Compare Match

When a compare match signal is generated, the timer output changes as specified by bits OS3 to
OS0 in TCSR. Figure 11.8 shows the timing when the timer output is toggled by the compare
match A signal.
P
Compare match A
signal
Timer output pin
Figure 11.8 Timing of Toggled Timer Output at Compare Match A
11.5.4

Timing of Counter Clear by Compare Match

TCNT is cleared when compare match A or B occurs, depending on the settings of bits CCLR1
and CCLR0 in TCR. Figure 11.9 shows the timing of this operation.
P
Compare match
signal
TCNT
Figure 11.9 Timing of Counter Clear by Compare Match
Rev.2.00 Jun. 28, 2007 Page 428 of 666
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