Bit Rate Register (Brr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
15.2.9

Bit Rate Register (BRR)

b7 b6
1 1
Value after reset:
BRR is an 8-bit register that adjusts the bit rate.
As each SCI channel has independent baud-rate generator control, different bit rates can be set for each. Table 15.4 lists
the relationships between the setting (N) in the BRR and the bit rate (B) for normal asynchronous mode, multi-processor
transfer, clock synchronous mode, and smart card interface mode.
The initial value of BRR is FFh.
BRR can be read from by the CPU at all times, but it can be written to only when the TE and RE bits in SCR are 0.
Table 15.4 Relationships between N Setting in BRR and Bit Rate B
Mode ABCS Bit in SEMR
Asynchronous,
multi-processor
transfer
Clock synchronous
Smart card interface
B: Bit rate (bps)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
P1 : Operating frequency (MHz)
φ
n and S: Determined by the SMR setting listed in the following table.
Table 15.5 Clock Source Settings
SMR Setting
CKS[1:0] Bits
0 0
0 1
1 0
1 1
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
b5 b4 b3 b2
1 1 1 1
BRR Setting
× 10
P1φ
0
N =
64 × 2 2n-1
P1φ × 10
N =
1
32 × 2 2n-1
P1φ × 10
N =
8 × 2 2n-1
P1φ × 10
N =
S × 2
2n+1
Clock Source
P1φ clock
P1φ/4 clock
P1φ/16 clock
P1φ/64 clock
b1 b0
1 1
6
–1
Error (%) = {
B × 64 × 2
× B
6
–1
Error (%) = {
× B
B × 32 × 2
6
–1
× B
6
Error (%) = {
–1
× B
15. Serial Communications Interface
Error
P1φ × 10
6
–1 } × 100
2n-1 × (N+1)
P1φ × 10 6
–1 } × 100
2n-1 × (N+1)
P1φ × 10 6
–1 } × 100
B × S × 2 2n+1 × (N+1)
n
0
1
2
3
15-17