Bit Rate Register (Brr); Table 12.2 Relationships Between N Setting In Brr And Bit Rate B - Renesas H8SX/1500 Series Hardware Manual

Section 12 Serial Communication Interface (SCI)
12.3.9

Bit Rate Register (BRR)

BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 12.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and
it can be read from or written to by the CPU at all times.

Table 12.2 Relationships between N Setting in BRR and Bit Rate B

Mode
Asynchronous mode
Clocked synchronous mode
Smart card interface mode
[Legend]
B: Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
N:
Pφ: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following table.
SMR Setting
CKS1 CKS0
0 0
0 1
1 0
1 1
Table 12.3 shows sample N settings in BRR in normal asynchronous mode. Table 12.4 shows the
maximum bit rate settable for each operating frequency. Tables 12.6 and 12.8 show sample N
settings in BRR in clocked synchronous mode and smart card interface mode, respectively. In
smart card interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be
selected. For details, see section 12.7.4, Receive Data Sampling Timing and Reception Margin.
Tables 12.5 and 12.7 show the maximum bit rates with external clock input.
Rev. 3.00 Mar. 14, 2006 Page 398 of 804
REJ09B0104-0300
Bit Rate
6
Pφ × 10
− 1
N =
2n – 1
64 × 2 × B
6
Pφ × 10
− 1
N =
2n – 1
8 × 2 × B
6
Pφ × 10
− 1
N =
2n + 1
S × 2 × B
n BCP1
0 0
1 0
2 1
3 1
Error
Pφ × 10
Error (%) = {
2n – 1
B × 64 × 2
Pφ × 10
{
Error (%) =
2n + 1
B × S × 2
SMR Setting
BCP0
0
1
0
1
6
– 1 } × 100
× (N + 1)
6
}
– 1 × 100
× (N + 1)
S
32
64
372
256