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16.2.8
Bit Rate Register (BRR)
Bit
:
Initial value
:
R/W
:
R/W
BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SMR.
BRR can be read or written to by the CPU at all times.
BRR is initialized to H'FF by a reset and in standby mode.
As baud rate generator control is performed independently for each channel, different values can
be set for each channel.
Table 16-3 shows sample BRR settings in asynchronous mode, and table 16-4 shows sample BRR
settings in clocked synchronous mode.
710
7
6
5
1
1
1
R/W
R/W
4
3
2
1
1
1
R/W
R/W
R/W
1
0
1
1
R/W
R/W
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