Bit Rate Register (Brr); Table 14.2 Relationships Between The N Setting In Brr And Bit Rate B - Renesas H8S Series Hardware Manual

14.3.9

Bit Rate Register (BRR)

BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 14.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read or written to by the CPU at all times.

Table 14.2 Relationships between the N Setting in BRR and Bit Rate B

Mode Bit Rate
Asynchronous
B =
Mode
Clocked
B =
Synchronous
Mode
Smart Card
B =
Interface Mode
Notes: B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following tables.
SMR Setting
CKS1 CKS0
0 0
0 1
1 0
1 1
Table 14.3 shows sample N settings in BRR in normal asynchronous mode. Table 14.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 14.6 shows sample N
settings in BRR in clocked synchronous mode. Table 14.8 shows sample N settings in BRR in
Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in
a 1-bit transfer interval) can be selected. For details, refer to section 14.7.4, Receive Data
Sampling Timing and Reception Margin in Smart Card Interface Mode. Tables 14.5 and 14.7
show the maximum bit rates with external clock input.
φ × 10
6
64 × 2 × (N + 1)
2n-1
φ × 10
6
8 × 2 × (N + 1)
2n-1
φ × 10
6
S × 2 × (N + 1)
2n+1
n
0
1
2
3
Section 14 Serial Communication Interface (SCI)
Error
Error (%) = {
B × 64 × 2
—
Error (%) = {
B × S × 2
SMR Setting
BCP1 BCP0
0 0
0 1
1 0
1 1
Rev. 6.00 Mar 15, 2006 page 331 of 570
φ × 10
6
− 1 } × 100
× (N + 1)
2n-1
φ × 10
6
− 1 } × 100
× (N + 1)
2n+1
S
32
64
372
256
REJ09B0211-0600