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13.2.8
Bit Rate Register (BRR)
BRR is an 8-bit register that., together with the CKS1 and CKS0 bits in SMR that select the baud
rate generator clock source, determines the serial communication bit rate.
7
Bit
1
Initial value
Read/Write
R/W
The CPU can always read and write BRR. BRR is initialized to H'FF by a reset and in standby
mode. Each SCI channel has independent baud rate generator control, so different values can be
set in the three channels.
Table 13.3 shows examples of BRR settings in asynchronous mode. Table 13.4 shows examples of
BRR settings in synchronous mode.
Table 13.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode
2
Bit Rate
n
N
Error (%) n
(bit/s)
110
1
141 0.03
150
1
103 0.16
300
0
207 0.16
600
0
103 0.16
1200
0
51
0.16
2400
0
25
0.16
4800
0
12
0.16
9600
0
6
–6.99
19200
0
2
8.51
31250
0
1
0.00
38400
0
1
–18.62
6
5
1
1
R/W
R/W
2.097152
N
Error (%) n
1
148 –0.04
1
108 0.21
0
217 0.21
0
108 0.21
0
54
–0.70
0
26
1.14
0
13
–2.48
0
6
–2.48
0
2
13.78
0
1
4.86
0
1
–14.67
Section 13 Serial Communication Interface
3
4
1
1
R/W
R/W
R/W
φ φ φ φ (MHz)
2.4576
N
Error (%) n
1
174 –0.26
1
127 0.00
0
255 0.00
0
127 0.00
0
63
0.00
0
31
0.00
0
15
0.00
0
7
0.00
0
3
0.00
0
1
22.88
0
1
0.00
Rev. 4.00 Jan 26, 2006 page 499 of 938
2
0
1
1
1
1
R/W
R/W
3
N
Error (%)
1
212 0.03
1
155 0.16
1
77
0.16
0
155 0.16
0
77
0.16
0
38
0.16
0
19
–2.34
0
9
–2.34
0
4
–2.34
0
2
0.00
—
—
—
REJ09B0276-0400
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