Contention Between Buffer Register Write And Compare Match - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.7.7

Contention between Buffer Register Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer
operation is the data after write.
Figure 10.102 shows the timing in this case.
P0φ
Address
Write signal
Compare match
signal
Compare match
buffer signal
Buffer register
TGR
Figure 10.102 Contention between Buffer Register Write and Compare Match
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
TGR write cycle
T1
T2
Buffer register
address
Buffer register write data
N M
N
10. Multi-Function Timer Pulse Unit 2
10-144