Conflict Between Buffer Register Write And Compare Match; Conflict Between Tgr Read And Input Capture; Figure 9.50 Conflict Between Buffer Register Write And Compare Match; Figure 9.51 Conflict Between Tgr Read And Input Capture - Renesas H8SX/1520 Series Hardware Manual

Section 9 16-Bit Timer Pulse Unit (TPU)
9.9.7

Conflict between Buffer Register Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the
buffer operation will be the write data.
Figure 9.50 shows the timing in this case.

Figure 9.50 Conflict between Buffer Register Write and Compare Match

9.9.8

Conflict between TGR Read and Input Capture

If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read
will be the data after input capture transfer.
Figure 9.51 shows the timing in this case.
Rev. 3.00 Mar. 14, 2006 Page 340 of 804
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Pφ
Address
Write
Compare match
signal
Buffer register
TGR
Pφ
Address
Read
Input capture
signal
TGR
Internal data
bus

Figure 9.51 Conflict between TGR Read and Input Capture

TGR write cycle
T1 T2
Buffer register
address
Data written to buffer register
N
M
M
TGR read cycle
T1 T2
TGR
address
X M
M