Conflict Between Frc Write And Increment; Figure 12.18 Frc Write-Increment Conflict - Renesas H8S/2158 User Manual

Section 12 16-Bit Free-Running Timer (FRT)
12.7.2

Conflict between FRC Write and Increment

If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes
priority and FRC is not incremented. Figure 12.18 shows the timing for this type of conflict.
Rev. 3.00 Jan 25, 2006 page 310 of 872
REJ09B0286-0300
Write cycle of FRC
T 1
φ
Address FRC address
Internal write
signal
FRC input
clock
FRC

Figure 12.18 FRC Write-Increment Conflict

T 2
N M
Write data