Input Capture Input Timing; Figure 10.7 Timing Of Input Capture Input Signal (Usual Case); Figure 10.8 Timing Of Input Capture Input Signal (When Icra To Icrd Are Read) - Renesas H8S/2437 Hardware Manual

10.5.4

Input Capture Input Timing

The rising or falling edge can be selected for the input capture input timing by the IEDGA to
IEDGD bits in TCR. Figure 10.7 shows the usual input capture timing when the rising edge is
selected.
φ
Input capture
input pin
Input capture signal

Figure 10.7 Timing of Input Capture Input Signal (Usual Case)

If the corresponding input capture signal is input when ICRA to ICRD are read, the input capture
signal is delayed by one system clock (φ). Figure 10.8 shows the timing for this case.
φ
Input capture
input pin
Input capture signal

Figure 10.8 Timing of Input Capture Input Signal (When ICRA to ICRD are Read)

Rev. 1.00, 09/03, page 254 of 704
Read cycle of ICRA to ICRD
T 1 T 2