Input Capture Signal Inputting Timing - Renesas Hitachi H8S/2194 Series Hardware Manual

17.3.5

Input Capture Signal Inputting Timing

(1) Input Capture Signal Inputting Timing
As for the input capture signal inputting, rising or falling edge is selected by settings of the
IEDGA through IEDGD bits of the TCRX.
Figure 17.7 shows the timing chart when the rising edge is selected (IEDGA through IEDGD
= 1).
Input capture signal
inputting pin
Input capture signal
Figure 17.7 Input Capture Signal Inputting Timing (under normal state)
(2) Input Capture Signal Inputting Timing when Making Buffer Operation
Buffer operation can be made using the ICRA or ICRD as the buffer of the ICRA or ICRB.
Figure 17.8 shows the input capture signal inputting timing chart in case both of the rising
and falling edges are designated (IEDGA = 1 and IEDGC = 0, or IEDGA = 0 and IEDGC =
1), using the ICRC as the buffer register for the ICRA (BUFEA = 1).
FTIA
Input capture
signal
FRC
ICRA
ICRC
Figure 17.8 Input Capture Signal Inputting Timing Chart Under the Buffer Mode
n n+1
M n
m M
(under normal state)
N
n N
M n
Rev. 2.0, 11/00, page 379 of 1037